Method and apparatus for controlling writing of flash EEPROM by microcomputer

• US 6,567,930 B1
• Filed: 11/12/1999
• Issued: 05/20/2003
• Est. Priority Date: 11/13/1998
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Moriya, Seiichi
• Primary Examiner(s): BADERMAN, SCOTT T
• Application Number:
  US09/438,771
• Time in Patent Office: 1,285 Days
• Field of Search: 714/23, 714/55, 710/262, 711/103, 711/166, 711/167
• US Class Current: 714/23
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06

Abstract

An apparatus that make it possible for a microcomputer to execute self-programming without the occurrence of shutdown or initialization (restart) includes a flash EEPROM for storing programs and data, a monitoring circuit for monitoring program runaway and malfunction, and the microcomputer. When rewriting of the content of said flash EEPROM (i.e., self-programming) is executed via control by the microcomputer, the monitoring circuit controls output/suppression of an abnormality detection signal on the basis of an externally entered flash EEPROM write-enable signal and a monitoring-circuit operation-control signal output from the microcomputer.

Claims

1. A method of controlling writing of a non-volatile memory electrically writable by a microcomputer, comprising:

(a) rewriting content of an electrically writable non-volatile memory for storing programs and data through self-programming via control by the microcomputer, and

(b) upon said rewriting (a), controlling a monitoring circuit for monitoring runaway or malfunction of a program executed by said microcomputer to inhibit output of an abnormality detection signal from said monitoring circuit based upon values of an externally entered write-enable signal for enabling writing of said non-volatile memory and of a monitoring circuit operation-control signal output from said microcomputer,

thereby making it possible to rewrite the content of said non-volatile member by said self-programming without shutting down or initializing said microcomputer.

2. A method of controlling writing of a flash EEPROM by a microcomputer, comprising:

(a) rewriting content of a flash EEPROM for storing programs and data through self-programming via control by the microcomputer, and

(b) upon said rewriting (a) controlling a monitoring circuit for monitoring runaway or malfunction of a program executed by said microcomputer to inhibit output of an abnormality detection signal from said monitoring circuit based upon values of an externally entered flash EEPROM write-enable signal and of a monitoring-circuit operation-control signal output from said microcomputer.

3. A control apparatus comprising at least a flash EEPROM for storing programs and data, a monitoring circuit for monitoring program runaway and malfunction, and a microcomputer, said control apparatus executing self-programming for rewriting the content of said flash EEPROM via control performed by said microcomputer,

said monitoring circuit having means, to which are input an externally entered flash EEPROM write-enable signal and a monitoring-circuit operation-control signal output from said microcomputer, for controlling output/suppression of an abnormal detection signal based upon values possessed by these signals;

wherein when rewriting of the content of said flash EEPROM is executed via control by said microcomputer, said monitoring circuit makes it possible to rewrite the content of said flash EEPRROM without shutting down or initializing said microcomputer.

4. The control apparatus according to claim 3, wherein said monitoring circuit comprises:

a watchdog timer for outputting the abnormality detection signal; and

means, to which are input the externally entered flash EEPROM write-enable signal and the monitoring-circuit operation-control signal output from said microcomputer, for exercising control so as to inhibit said watchdog timer from outputting the abnormality detection signal.

5. A control apparatus comprising:

a flash EEPROM for storing programs and data;

a microcomputer; and

a monitoring circuit having a watchdog timer,

wherein in a case where said watchdog timer receives a monitor signal from said microcomputer, resets its count, starts counting a clock and is supplied with the monitor signal from said microcomputer before attaining a predetermined count, said watchdog timer resets its count and starts counting the clock again; and

in a case where said watchdog timer receives the monitor signal from said microcomputer, resets its count, starts counting the clock and the attains the predetermined count without input of the monitor signal from said microcomputer, said watchdog timer outputs an abnormality detection signal;

content of said flash EEPROM being rewritten via a control operation performed by said microcomputer;

said monitoring circuit having control means, to which are input an externally entered flash EEPROM write-enable signal and a monitoring-circuit operation-halt signal output from said microcomputer, for exercising control so as to inhibit said watchdog timer from outputting the abnormality detection signal when the monitoring-circuit operation-halt signal is active; and

wherein when rewriting of the content of said flash EEPROM is executed via control by said microcomputer, said monitoring circuit makes it possible to rewrite the content of said flash EEPROM without outputting the abnormality detection signal to said microcomputer and, hence, without shutting down or initializing said microcomputer.

6. A microcomputer internally incorporating:

a flash EEPROM for storing programs and data;

a processor;

a monitoring circuit having a watchdog timer; and

peripheral circuitry;

wherein in a case where said watchdog timer receives a monitor signal from said processor, resets its count, starts counting a clock and is supplied with the monitor signal from said processor before attaining a predetermined count, said watchdog timer resets its count and starts counting the clock again; and

in a case where said watchdog timer receives the monitor signal from said processor, resets its count, starts counting the clock and the attains the predetermined count without input of the monitor signal from said processor, said watchdog timer outputs an abnormality detection signal;

wherein content of said flash EEPROM is rewritten via a control operation performed by said processor;

wherein said monitoring circuit has control means, to which are input an externally entered flash EEPROM write-enable signal and a monitoring-circuit operation-halt signal output from said processor, for exercising control so as to inhibit said watchdog timer from outputting the abnormality detection signal when the monitoring-circuit operation-halt signal is active;

wherein when rewriting of the content of said flash EEPROM is executed via control by said processor, said monitoring circuit makes it possible to rewrite the content of said flash EEPROM without outputting the abnormality detection signal to said processor and, hence, without shutting down or initializing said processor.