System and method for communicating with an integrated circuit

• US 6,567,932 B2
• Filed: 10/01/1999
• Issued: 05/20/2003
• Est. Priority Date: 10/01/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Edwards, David Alan, Rich, Anthony Willis
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): Duncan, Marc M
• Application Number:
  US09/411,795
• Publication Number:
  US 20030056154A1
• Time in Patent Office: 1,327 Days
• Field of Search: 714/25, 714/30, 714/34, 714/724, 714/733, 713/400, 716/1, 716/4, 326/16
• US Class Current: 714/30
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/364 tracing values on a bus
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

Claims

1. An integrated circuit comprising;

a communication circuit having a communication link coupling the integrated circuit and an external system, wherein the communication circuit is configured to transmit at least one of a group of messages including;

a request message including a first system bus command for accessing a first storage location in a memory of the external system;

a response message including data produced in response to a second system bus command; and

a trace message, wherein the trace message is an unsolicited message sent to the external system.

2. The integrated circuit according to claim 1, wherein the request message includes:

an address of the memory location of the external system;

an opcode defining the content of the request message;

source information identifying a source of the request message; and

request data upon which the external system will operate.

3. The integrated circuit according to claim 2, wherein the request message opcode indicates that the request message is at least one type of the following group of messages:

a read request to read data stored at the location of the external system;

a write request to write data to the storage location; and

a swap request to swap request data with data stored at the storage location.

4. The integrated system according to claim 1, wherein the response message includes:

source information identifying a source of the request message; and

response data requested by the external system.

5. The integrated circuit according to claim 1, wherein the communication circuit is configured to receive at least one of a group of messages including:

a request message including the second system bus command for accessing a second storage location associated with the integrated circuit; and

a response message including data produced in response to the first system bus command.

6. The integrated circuit according to claim 1, wherein the communication link comprises a plurality of signals including:

an output data signal;

an output clocking signal by the external system to extract output from the output data signal;

an input data signal; and

an input clocking signal used by the integrated circuit to extract input data from the input data signal.

7. The integrated circuit according to claim 6, wherein the communication link further comprises an output synchronization signal indicating that the output data signal includes valid data.

8. The integrated circuit according to claim 6, wherein the output data is synchronous to a rising edge of the output clocking signal.

9. The integrated circuit according to claim 6, wherein the output clocking signal has a frequency which is proportional to a frequency of a system bus associated with the integrated circuit.

10. The integrated circuit according to claim 6, wherein the communication link further comprises an output synchronization signal indicating at least one of a group of:

an output idle condition; and

a start of an output data transfer.

11. The integrated circuit according to claim 6, wherein the output clocking signal has a frequency value in a range from zero to 100 MHz.

12. The integrated circuit according to claim 6, wherein the communication link further comprises a plurality of status signals indicating a power status of the integrated circuit.

13. The integrated circuit according to claim 12, wherein the status signals indicate at least one of the group of states including:

a normal operating state;

a standby state wherein a processor associated with the integrated circuit is not currently executing instructions;

a sleep state wherein the processor is not currently executing instructions, and one or more modules associated with the integrated circuit are operating; and

a module standby state wherein the one or more modules associated with the integrated circuit are powered down.

14. An integrated circuit comprising:

a communication circuit having a communication link coupling the integrated circuit and an external system, wherein the communication link comprises a plurality of signals including;

an output data signal;

an output clocking signal by the external system to extract output from the output data signal;

an input data signal; and

an input clocking signal used by the integrated circuit to extract input data from the input data signal, wherein the output clocking signal is produced by a divider circuit from a system bus clocking signal and a divider value, wherein the communication circuit is configured to transmit at least one of a group of messages including;

a request message including a first system bus command for accessing a first storage location in a memory of the external system;

a response message including data produced in response to a second system bus command; and

a trace message.

15. The integrated circuit according to claim 14, wherein the divider value is stored in a register associated with the integrated circuit.