PLD configuration architecture

• US 6,567,970 B1
• Filed: 12/27/2000
• Issued: 05/20/2003
• Est. Priority Date: 12/27/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Nayak, Anup, Lulla, Navaz, Ighani, Ramin, Nema, Rajiv
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): TAT, BINH C
• Application Number:
  US09/751,234
• Time in Patent Office: 874 Days
• Field of Search: 716/16, 716/17, 716/18, 716/20, 716/19, 395/500, 326/40, 326/41, 326/42
• US Class Current: 326/38
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

An apparatus comprising one or more configuration blocks. The configuration blocks (i) may comprise a number of configuration elements and (ii) may be configured to initiate reading or writing of the configuration elements in response to a control input.

Claims

1. An apparatus comprising:

a global bus;

one or more configuration blocks each (i) comprising a number of configuration elements and (ii) configured to initiate reading or writing of said configuration elements in response to a control input, wherein data received from said global bus is written to said configuration elements in a first mode and data read from said configuration elements is presented to said global bus in a second mode; and

a control circuit configured to (i) generate said control input and (ii) present said data to and receive said data from said global bus.

2. The apparatus according to claim 1, wherein said reading and writing transfers said data between said one or more configuration blocks and said global bus in response to one or more global control signals.

3. The apparatus according to claim 1, wherein each of said configuration blocks is further configured to generate a status output.

4. The apparatus according to claim 3, wherein said status output of each of said configuration blocks is presented as said control input of a next configuration block.

5. The apparatus according to claim 3, wherein said control input and said status output comprise handshaking signals.

6. The apparatus according to claim 1, wherein said reading and writing of said configuration elements are synchronous operations.

7. The apparatus according to claim 2, wherein:

said control circuit is further configured to (i) present said control input to a first one of said one or more configuration blocks, (ii) generate said global control signals, and (iii) receive said status output presented by a last one of said one or-more configuration blocks.

8. The apparatus according to claim 7, wherein the same configuration block receives said control input and presents said status output.

9. The apparatus according to claim 1, wherein said configuration blocks are heterogeneous.

10. The apparatus according to claim 9, wherein one or more of said configurations blocks comprise a PLD type block.

11. The apparatus according to claim 9, wherein one or more of said configurations blocks comprise an embedded memory block.

12. The apparatus according to claim 11, wherein said embedded memory block comprises random access memory.

13. The apparatus according to claim 9, wherein said configuration blocks comprise the same or different numbers of configuration elements.

14. The apparatus according to claim 1, wherein said apparatus comprises a programmable logic device.

15. The apparatus according to claim 1, wherein one or more of said configuration blocks comprise a one-hot shift register configured to control said reading and writing of said configuration elements.

16. The apparatus according to claim 1, wherein one or more of said configuration blocks comprise a shift register configured to transfer data between said configuration elements and said global bus.

17. The apparatus according to claim 1, wherein said apparatus is part of an integrated circuit.

18. A method for configuring a programmable logic device, comprising the steps of:

(A) initiating configuration or verification of one or more configuration blocks in response to a first control signal;

(B) programming a number of configuration elements of said one or more configuration blocks with data received from a global bus in a first mode and reading data from said number of configuration elements and presenting said read data to said global bus for verification in a second mode; and

(C) generating a second control signal when said configuration or verification of said one or more configuration blocks is complete.

19. The method according to claim 18, further comprising the step of:

(D) repeating steps A-C on a next configuration block.

20. The method according to claim 19, further comprising the step of:

(E) terminating configuration or verification of said programmable logic device when step C is completed on a last configuration block.

21. A programmable logic device comprising:

means for configuring said programmable logic device arranged as one or more configuration blocks, wherein data received from a global bus is written -to said configuration blocks in a first mode and data read from said configuration blocks is presented to said global bus in a second mode;

means for initiating said writing or reading of each of said one or more configuration blocks in response to a control input and indicating completion of said reading and writing; and

means for generating said control input and (ii) presenting said data to and receiving said data from said global bus.