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Membrane partition system for plating of wafers

  • US 6,569,299 B1
  • Filed: 05/18/2000
  • Issued: 05/27/2003
  • Est. Priority Date: 11/13/1997
  • Status: Expired due to Term
First Claim
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1. An electroplating system for semiconductor wafers comprising:

  • a power supply having a negative terminal and a positive terminal;

    a semiconductor wafer electrically connected to the negative terminal;

    a plating bath holding a plating solution;

    an anode positioned in the plating solution and electrically connected to the positive terminal;

    a pump for creating a flow of plating solution generally in a direction from the anode towards the wafer; and

    a porous membrane positioned downstream from the anode in the flow of plating solution.

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