Semiconductor metal interconnect reliability test structure

• US 6,570,181 B1
• Filed: 10/24/2000
• Issued: 05/27/2003
• Est. Priority Date: 12/07/1999
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Graas, Carole D., Ting, Larry
• Primary Examiner(s): Tran, Minh Loan
• Application Number:
  US09/695,374
• Time in Patent Office: 945 Days
• Field of Search: 257/48, 257/786, 257/773, 257/774, 438/11, 438/14, 438/16, 438/18, 324/765
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A semiconductor reliability test structure (10) is formed on a face of a semiconductor substrate. The test structure (10) includes a chain of a plurality of long test links (12) formed of a first semiconductor material, where the plurality of long test links (12) is alternately interconnected by a plurality of short connecting links (14) formed of a second semiconductor material. The test structure (10) further includes first and second bond pads (20, 22) coupled to the first and second ends of the chain, respectively.

Claims

1. A semiconductor reliability test structure formed on a face of a semiconductor substrate, comprising:

a chain including a plurality of long test links formed of a first semiconductor material, the plurality of long test links being alternately interconnected by a plurality of short connecting links formed of a second semiconductor material, the chain having first and second ends wherein the long test links are formed in a first layer and the short connecting links are formed in a second layer,

a plurality of vias connecting the first and second layers of the long and short connecting links; and

first and second bond pads coupled to the first and second ends of the chain, respectively.

2. The test structure, as set forth in claim 1, wherein the first and second bond pads are formed from the second layer.

3. The test structure, as set forth in claim 1, wherein the plurality of long test links are aligned along a first axis and the plurality of short connecting links are aligned along a second axis.

4. The test structure, as set forth in claim 1, wherein the plurality of long test links are aligned along a first axis and the plurality of short connecting links are aligned along a second axis perpendicular to the first axis.

5. The test structure, as set forth in claim 1, further comprising at least one intermediate bond pad coupled to a short connecting link.

6. The test structure, as set forth in claim 1, further comprising at least one intermediate bond pad coupled to a short connecting link substantially at a mid-point of the chain.

7. The test structure, as set forth in claim 1, further comprising:

at least one tap coupled to a short connecting link in the chain; and

at least one intermediate bond pad coupled the tap.

8. The test structure, as set forth in claim 1, further comprising a laser focus pad formed on the face of the semiconductor substrate.

9. The test structure, as set forth in claim 1, further comprising a laser focus pad formed on the face of the semiconductor substrate adjacent to one of the first and second ends of the chain.

10. The test structure, as set forth in claim 1, further comprising a plurality of tick marks formed on the face of the semiconductor substrate providing a location reference for positions in the plurality of long test links.

11. A semiconductor metal interconnect reliability test structure formed on a face of a semiconductor substrate, comprising:

a chain including a plurality of long test links formed in a first metal layer, the plurality of long test links being alternately interconnected by a plurality of short connecting links formed in a second metal layer, the chain having first and second ends;

first and second bond pads formed in the second metal layer and coupled to the first and second ends of the chain, respectively;

a plurality of vias connecting the first and second metal layers of the long and short connecting links; and

the plurality of long test links being generally aligned along a first axis and the plurality of short connecting links being generally aligned along a second axis, the alternating long test links and short connecting links generally forming a serpentine configuration.

12. The test structure, as set forth in claim 11, further comprising at least one intermediate bond pad coupled to a short connecting link.

13. The test structure, as set forth in claim 11, further comprising at least one intermediate bond pad coupled to a short connecting link substantially at a mid-point of the chain.

14. The test structure, as set forth in claim 11, further comprising:

at least one tap coupled to a short connecting link in the chain; and

at least one intermediate bond pad coupled the tap.

15. The test structure, as set forth in claim 11, further comprising a laser focus pad formed on the face of the semiconductor substrate adjacent to one of the first and second ends of the chain.

16. The test structure, as set forth in claim 11, further comprising a plurality of tick marks formed on the face of the semiconductor substrate providing a location reference for positions in the plurality of long test links.

17. A semiconductor metal interconnect reliability test structure formed on a face of a semiconductor substrate, comprising:

a chain including a plurality of long test links formed in a first metal layer, the plurality of long test links being alternately interconnected by a plurality of short connecting links formed in a second metal layer, the chain having first and second ends;

first and second bond pads formed in the second metal layer and coupled to the first and second ends of the chain, respectively;

a plurality of vias connecting the first and second metal layers of the long and short connecting links;

the plurality of long test links being aligned along a first axis and the plurality of short connecting links being aligned along a second axis, the alternating long and short connecting links generally forming a serpentine configuration; and

at least one intermediate bond pad coupled to a short connecting link; and

a plurality of tick marks formed on the face of the semiconductor substrate thereby providing a location reference for positions in the plurality of long test links.

18. The test structure, as set forth in claim 17, further comprising a laser focus pad formed on the face of the semiconductor substrate adjacent to one of the first and second ends of the chain.