Semiconductor metal interconnect reliability test structure
First Claim
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1. A semiconductor reliability test structure formed on a face of a semiconductor substrate, comprising:
- a chain including a plurality of long test links formed of a first semiconductor material, the plurality of long test links being alternately interconnected by a plurality of short connecting links formed of a second semiconductor material, the chain having first and second ends wherein the long test links are formed in a first layer and the short connecting links are formed in a second layer, a plurality of vias connecting the first and second layers of the long and short connecting links; and
first and second bond pads coupled to the first and second ends of the chain, respectively.
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Abstract
A semiconductor reliability test structure (10) is formed on a face of a semiconductor substrate. The test structure (10) includes a chain of a plurality of long test links (12) formed of a first semiconductor material, where the plurality of long test links (12) is alternately interconnected by a plurality of short connecting links (14) formed of a second semiconductor material. The test structure (10) further includes first and second bond pads (20, 22) coupled to the first and second ends of the chain, respectively.
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Citations
18 Claims
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1. A semiconductor reliability test structure formed on a face of a semiconductor substrate, comprising:
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a chain including a plurality of long test links formed of a first semiconductor material, the plurality of long test links being alternately interconnected by a plurality of short connecting links formed of a second semiconductor material, the chain having first and second ends wherein the long test links are formed in a first layer and the short connecting links are formed in a second layer, a plurality of vias connecting the first and second layers of the long and short connecting links; and
first and second bond pads coupled to the first and second ends of the chain, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
at least one tap coupled to a short connecting link in the chain; and
at least one intermediate bond pad coupled the tap.
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8. The test structure, as set forth in claim 1, further comprising a laser focus pad formed on the face of the semiconductor substrate.
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9. The test structure, as set forth in claim 1, further comprising a laser focus pad formed on the face of the semiconductor substrate adjacent to one of the first and second ends of the chain.
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10. The test structure, as set forth in claim 1, further comprising a plurality of tick marks formed on the face of the semiconductor substrate providing a location reference for positions in the plurality of long test links.
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11. A semiconductor metal interconnect reliability test structure formed on a face of a semiconductor substrate, comprising:
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a chain including a plurality of long test links formed in a first metal layer, the plurality of long test links being alternately interconnected by a plurality of short connecting links formed in a second metal layer, the chain having first and second ends;
first and second bond pads formed in the second metal layer and coupled to the first and second ends of the chain, respectively;
a plurality of vias connecting the first and second metal layers of the long and short connecting links; and
the plurality of long test links being generally aligned along a first axis and the plurality of short connecting links being generally aligned along a second axis, the alternating long test links and short connecting links generally forming a serpentine configuration. - View Dependent Claims (12, 13, 14, 15, 16)
at least one tap coupled to a short connecting link in the chain; and
at least one intermediate bond pad coupled the tap.
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15. The test structure, as set forth in claim 11, further comprising a laser focus pad formed on the face of the semiconductor substrate adjacent to one of the first and second ends of the chain.
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16. The test structure, as set forth in claim 11, further comprising a plurality of tick marks formed on the face of the semiconductor substrate providing a location reference for positions in the plurality of long test links.
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17. A semiconductor metal interconnect reliability test structure formed on a face of a semiconductor substrate, comprising:
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a chain including a plurality of long test links formed in a first metal layer, the plurality of long test links being alternately interconnected by a plurality of short connecting links formed in a second metal layer, the chain having first and second ends;
first and second bond pads formed in the second metal layer and coupled to the first and second ends of the chain, respectively;
a plurality of vias connecting the first and second metal layers of the long and short connecting links;
the plurality of long test links being aligned along a first axis and the plurality of short connecting links being aligned along a second axis, the alternating long and short connecting links generally forming a serpentine configuration; and
at least one intermediate bond pad coupled to a short connecting link; and
a plurality of tick marks formed on the face of the semiconductor substrate thereby providing a location reference for positions in the plurality of long test links. - View Dependent Claims (18)
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Specification