High-voltage transistor with multi-layer conduction region

• US 6,570,219 B1
• Filed: 05/17/2000
• Issued: 05/27/2003
• Est. Priority Date: 11/05/1996
• Status: Expired due to Term

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald R., Ajit, Janardhanan S., Rumennik, Vladimir
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US09/574,563
• Time in Patent Office: 1,105 Days
• Field of Search: 257/342, 257/343, 257/341, 257/314, 257/328, 257/344, 257/488, 257/492, 257/493, 257/495, 257/262, 257/339, 257/335, 257/336
• US Class Current: 257/343
• CPC Class Codes: H01L 21/26 Bombardment with radiation H01L21/3105 takes precedence
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Claims

1. A high voltage field-effect transistor (HVFET) comprising:

a substrate of a first conductivity type;

a first region of a second conductivity type disposed within the substrate;

a source diffusion region disposed in the substrate spaced-apart from the first region, an IGFET channel region being formed between the source diffusion region and the first region;

a drain diffusion region disposed in the first region;

a buried region of said first conductivity type disposed within the first region, the buried region forming JFET channels within the first region, one of said JFET channels being formed above the buried region with a doped impurity concentration of approximately 1×

10¹²/cm² and another of said JFET channels below the buried region, the buried region being spaced-apart from the drain diffusion region;

an insulated gate formed above the IGFET channel region.

2. The HVFET according to claim 1 wherein the first region has a first surface that borders a surface of the substrate.

3. The HVFET according to claim 1 further comprising:

a second buried region of the first conductivity type disposed beneath the source diffusion region.

4. The HVFET according to claim 3 wherein the second buried region extends laterally under the IGFET channel region.

5. The HVFET according to claim 1 wherein the buried region comprises a plurality of buried layers that form a corresponding plurality of JFET channels.

6. The HVFET according to claim 1, further comprising:

a second region of the first conductivity type disposed in the substrate adjacent to the source diffusion region.

7. The HVFET according to claim 1, further comprising:

a source electrode connected to the source diffusion region; and

a drain electrode connected to the drain diffusion region.

8. The HVFET according to claim 7 wherein the source and drain electrodes include field plate members.

9. The HVFET according to claim 1 further comprising:

a tap diffusion region of the second conductivity type disposed in the first region near a perimeter boundary of the first region.

10. The HVFET according to claim 1 wherein the first region is disposed in an epitaxial layer.

11. The HVFET according to claim 1 wherein the buried region includes one or more openings that connect the one and the another of the JFET channels.

12. The HVFET according to claim 1 wherein the first and second conductivity types are p-type and n-type, respectively.

13. The HVFET according to claim 1 wherein the source diffusion region has a source fingertip area, and the first region has a pair of drain fingertip areas inter-digitated with the source fingertip area, the drain diffusion region being disposed in the pair of drain fingertip areas of the first region.

14. The HVFET according to claim 13 further comprising a buffer region disposed between the source diffusion region and the first region about the source fingertip area, the buffer region being substantially wider than the IGFET channel region.

15. The HVFET according to claim 1 wherein the buried region has a doped impurity concentration approximately twice that of said one of said JFET channels above the buried region.

16. The HVFET according to claim 15 wherein the buried region has a doped impurity concentration of approximately 2×

10¹²/cm².

17. The HVFET according to claim 16 wherein said another of said JFET channels below the buried region channel has a doped impurity concentration of approximately 2×

10¹²/cm².

18. The HVFET according to claim 1 wherein the one JFET channel has a thickness of 0.5 microns to 1.0 microns.

19. The HVFET according to claim 1 wherein the buried layer has a thickness of 1.0 microns to 1.5 microns.

20. A high voltage field-effect transistor (HVFET) comprising:

a substrate of a first conductivity type;

a first region of a second conductivity type disposed in the substrate, the first region having a laterally extended portion that forms a lateral boundary with the substrate;

a drain diffusion region of the second conductivity type disposed in the first region and separated from the lateral boundary by the laterally extended portion;

a second region of the first conductivity type disposed in the substrate;

a source diffusion region of the second conductivity type disposed in the second region, a channel region being formed between the source diffusion region and the lateral boundary;

an insulated gate disposed above the channel region;

a buried region of the first conductivity type sandwiched within the laterally extended portion of the first region to form a junction field-effect device in which current flows in the first region both above and below the buried region, a doped impurity concentration in the first region above the buried region being about 1×

10¹²/cm² wherein the buried region is spaced-apart from the drain diffusion region.

21. The HVFET according to claim 20 wherein the insulated gate extends laterally over the substrate from the source diffusion region to the lateral boundary.

22. The HVFET according to claim 20 wherein the second region is spaced-apart from the lateral boundary.

23. The HVFET according to claim 20 wherein the first region comprises an epitaxial layer.

24. The HVFET according to claim 20 wherein the buried region is connected to the substrate.

25. The HVFET according to claim 20 wherein the buried region is spaced-apart from the lateral boundary.

26. The HVFET according to claim 20 wherein the first and second conductivity types are p-type and n-type, respectively.

27. The HVFET according to claim 20 wherein the first and second conductivity types are n-type and p-type, respectively.

28. The HVFET according to claims 20, 21, 22, 23, 24, 25, 26 or 27 further comprising:

an additional diffusion region of the first conductivity type disposed in the second region adjacent the source diffusion region.

29. The HVFET according to claim 20 further comprising a source electrode connected to the source diffusion region, the source electrode including a source field plate member that at least partially overlaps the buried region.

30. The HVFET according to claim 20 wherein the buried region has a doped impurity concentration approximately twice that of the first region above the buried layer.

31. The HVFET according to claim 30 wherein the buried region has a doped impurity concentration of approximately 2×

10²/cm².

32. The HVFET according to claim 31 wherein the first region below the buried layer has a doped impurity concentration of approximately 2×

10¹²/cm².

33. The HVFET according to claim 32 wherein the buried layer is disposed in the first region about 0.5 to 1.0 microns below a surface of the substrate.

34. The HVFET according to claim 33 wherein the buried layer has a thickness of 1.0 microns to 1.5 microns.

35. A high voltage field-effect transistor (HVFET) comprising:

a substrate of a first conductivity type;

a first region of a second conductivity type disposed in the substrate, the first region having a laterally extended portion that forms a lateral boundary with the substrate;

a drain diffusion region of the second conductivity type disposed in the first region and separated from the lateral boundary by the laterally extended portion;

a source diffusion region of the second conductivity type disposed in the substrate and spaced-apart from the lateral boundary of the first region, a channel region being formed between the source diffusion region and the lateral boundary;

an insulated gate disposed above the channel region;

a first buried layer of the first conductivity type disposed in the substrate beneath the source diffusion region;

a second buried layer of the first conductivity type sandwiched within the laterally extended portion of the first region and spaced-apart from the lateral boundary so as to act as an effective gate controlling dual current channels in the first region both above and below the second buried layer, a doped impurity concentration in the first region above the second buried layer being about 1×

10¹²/cm², wherein the second buried layer is spaced-apart from the drain diffusion region.

36. The HVFET according to claim 35 wherein the insulated gate extends laterally over the substrate from the source diffusion region to the lateral boundary.

37. The HVFET according to claim 35 wherein the insulated gate extends laterally over the substrate from the source diffusion region to the second buried layer.

38. The HVFET according to claim 35 wherein the first buried layer is spaced-apart from the lateral boundary.

39. The HVFET according to claim 35 wherein the first and second conductivity types are p-type and n-type, respectively.

40. The.HVFET according to claim 35 wherein the first and second conductivity types are n-type and p-type, respectively.

41. The HVFET according to claims 35, 36, 37, 38, 39 or 40 further comprising

an additional diffusion region of the first conductivity type disposed in the substrate adjacent the source diffusion region.

42. The HVFET according to claim 35 further comprising a source electrode connected to the source diffusion, region, the source electrode including a source field plate member that at least partially overlaps the second buried layer.

43. The HVFET according to claim 35 wherein the second buried layer has a doped impurity concentration approximately twice that of the first region above the second buried layer.

44. The HVFET according to claim 43 wherein the second buried layer has a doped impurity concentration of approximately 2×

10¹²/cm².

45. The HVFET according to claim 44 wherein the first region below the second buried layer has a doped impurity concentration of approximately 2×

10¹²/cm².

46. The HVFET according to claim 35 wherein the second buried layer is disposed in the first region about 0.5 to 1.0 microns below a surface of the substrate.

47. The HVFET according to claim 46 wherein the second buried layer has a thickness of 1.0 microns to 1.5 microns.

48. A high voltage field-effect transistor (HVFET) comprising:

a substrate of a first conductivity type;

a first region of a second conductivity type disposed within the substrate;

a source diffusion region of the second conductivity type disposed in the substrate spaced-apart from the first region, a channel-region being formed in the substrate between the source diffusion region and the-first region;

a source electrode connected to the source diffusion region;

a drain diffusion region of the second conductivity type disposed within the first region;

a drain electrode connected to the drain diffusion region;

a buried region of the first conductivity type disposed within the first region, a first conduction channel being formed above the buried region and a second conduction channel being formed below the buried region, the first conduction channel having a doped impurity concentration of 1×

10¹²/cm², the buried region being spaced-apart from the drain diffusion region; and

an insulated gate formed over the channel region.

49. The HVFET according to claim 48 further comprising:

a second region of the first conductivity type disposed within the substrate, the source diffusion region being disposed within the second region.

50. The HVFET according to claim 49 further comprising

a third region of the first conductivity type disposed in the second region adjacent to the source diffusion region.

51. The HVFET according to claim 48 wherein the buried region is connected to the substrate.

52. The HVFET of claim 48 further comprising:

a tap diffusion region of the second conductivity type disposed in the first region near a perimeter boundary of the first region.

53. The HVFET according to claim 48 further comprising:

a second buried region of the first conductivity type disposed within the substrate beneath the source diffusion region.

54. The HVFET according to claim 53 wherein the second buried region extends laterally to a region under the channel region.

55. The HVFET according to claim 48 wherein the first and second conductivity types are p-type and n-type, respectively.

56. The HVFET according to claim 48 wherein the buried region includes one or more openings that connect the first and second conduction channels.

57. The HVFET according to claim 48 wherein the source and drain electrodes include field plate members.

58. The HVFET according to claim 48 wherein the buried region comprises a plurality of buried layers that form a corresponding plurality of conduction channels.