Bonding of silicon wafers

• US 6,570,221 B1
• Filed: 07/27/1993
• Issued: 05/27/2003
• Est. Priority Date: 07/27/1993
• Status: Expired due to Fees

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Hyundai Electronics America Incorporated (SK Hynix Inc.)
• Inventors: Allman, Derryl D. J.
• Primary Examiner(s): ECKERT II, GEORGE C
• Application Number:
  US08/097,183
• Time in Patent Office: 3,591 Days
• Field of Search: 257/67, 257/68, 257/69, 257/723, 257/724, 257/725, 257/726, 257/727, 257/777, 257/347
• US Class Current: 257/347
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: Y10S 438/974 Substrate surface preparation

Abstract

The invention concerns the use of spin-on-glass (SOG) to bond two layers of semiconductor together, in order to form a Silicon-on-Insulator (SOI) structure. One type of SOG is a cross-linked siloxane polymer, preferably of the poly-organo-siloxane type, comprising a carbon content of at least 5 atomic weight percent.

Claims

1. A multi-layer semiconductor, comprising:

a first semiconductor wafer comprising a micro-machined sensor;

a second semiconductor wafer comprising a surface;

a second semiconductor device on the surface; and

a layer of cross-linked siloxane polymer sandwiched between the first semiconductor wafer and the surface, wherein;

the layer of cross-linked siloxane polymer bonds the first and second semiconductor wafers together; and

the layer of cross-linked siloxane polymer is formed through spin-on-glass.

2. The multi-layer semiconductor according to claim 1, wherein one of the first and second semiconductor wafers is between 0.1 micron and 675 microns thick.

3. The multi-layer semiconductor according to claim 1, wherein at least one of the first and second semiconductor wafers comprises single-crystal silicon.

4. The multi-layer semiconductor according to claim 1, wherein the layer of cross-linked siloxane polymer comprises a plurality of siloxane polymer layers which are successively formed.

5. The multi-layer semiconductor according to claim 4, wherein the apparatus is cured at a temperature of about 80 degrees C. between applying each of the plurality of siloxane polymer layers.

6. The multi-layer semiconductor according to claim 1, wherein one of the first and second semiconductor wafers is less than 10 microns thick.

7. The multi-layer semiconductor according to claim 1, wherein at least one of the first and second semiconductor wafers comprises integrated circuits.

8. The multi-layer semiconductor according to claim 1, wherein the cross-linked siloxane polymer is of the poly-organo-siloxane type, comprising a carbon content of at least 5 atomic weight percent.

9. The multi-layer semiconductor according to claim 1, wherein the micro-machined sensor is at least one of a diaphragm pressure sensor, a cantilevered acceleration sensor and a cantilevered flow sensor.

10. A multi-layer integrated semiconductor, comprising:

a first silicon substrate, wherein the first silicon substrate comprises a micro-machined sensor;

a second silicon substrate;

a layer on the second silicon substrate, wherein the layer comprises a transistor; and

a third layer comprising a highly cross-linked siloxane polymer, which bonds the first silicon substrate and the layer together, wherein the third layer of highly cross-linked siloxane polymer is formed through spin-on-glass.

11. The multi-layer integrated circuit according to claim 10, wherein the highly cross-linked siloxane polymer is of the poly-organo-siloxane type, comprising a carbon content of at least 5 atomic weight percent.

12. The multi-layer integrated circuit according to claim 10, wherein the third layer of highly cross-linked siloxane polymer comprises a plurality of siloxane polymer layers which are successively formed.

13. The multi-layer integrated circuit according to claim 12, wherein the integrated circuit is cured at a temperature of about 80 degrees C. between applying each of the plurality of siloxane polymer layers.

14. The multi-layer integrated circuit according to claim 10, further comprising three or more wafers with highly cross-linked siloxane polymer between each of the three or more wafers.

15. The multi-layer integrated circuit according to claim 10, further comprising vias which couple the micro-machined sensor to the transistor, wherein the vias penetrate the layer of highly cross-linked siloxane polymer.

16. The multi-layer electronic device according to claim 10, wherein the micro-machined sensor is at least one of a diaphragm pressure sensor, a cantilevered acceleration sensor and a cantilevered flow sensor.

17. A multi-layer semiconductor, comprising:

a first semiconductor wafer comprising a micro-machined device;

a second semiconductor wafer comprising a surface;

a second semiconductor device on the surface; and

a layer of cross-linked siloxane polymer bonding the first semiconductor wafer and the surface together, wherein the layer of cross-linked siloxane polymer is formed as spin-on-glass.