Radiation resistant integrated circuit design

• US 6,570,234 B1
• Filed: 11/17/2000
• Issued: 05/27/2003
• Est. Priority Date: 11/17/1999
• Status: Expired due to Term

• Current Assignee: Aeroflex Colorado Springs Incorporated (Cobham PLC)
• Original Assignee: Aeroflex UTMC Microelectronics Systems Incorporated
• Inventors: Gardner, Harry
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Farahani, Dana
• Application Number:
  US09/715,819
• Time in Patent Office: 921 Days
• Field of Search: 257/390, 257/213, 257/288, 257/297, 257/364, 257/365, 257/369, 257/372, 257/374, 257/379, 257/391, 257/394, 257/401, 257/406, 257/519, 257/547, 257/648, 257/921, 257/375, 257/314, 257/315, 257/318, 257/319
• US Class Current: 257/390
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Annular transistors are positioned with respect to the n-well diffusion region so that the active channels of the transistors are completely within the diffusion region, thereby avoiding the formation of the edges at the boundary between n⁺ active channel regions and adjacent field oxide region (the bird'"'"'s beak region), which are susceptible to the effect of the ionizing radiation. The edgeless design of the gate arrays reduces the degradation of the transistors caused by the bird'"'"'s beak leakage, while allowing for an unmodified commercial process flow for fabrication. An outer annular transistor and one or more inner annular transistors may be provided. The outer transistor may be used as an active transistor in the formation of logic circuits, or may provide isolation for the one or more inner transistors, which may be connected to form logic circuits. The design preferably includes a provision for readily disabling the radiation resistant system so the same design can be easily transformed into a non-radiation resistant design. Other electrical components such as a resistor may be formed with another annular gate electrode to isolate the component from the deleterious effects of ionizing radiation, as well.

Claims

1. A radiation hardened integrated circuit device on a semiconductor substrate, comprising:

an outer annular transistor having an outer annular gate electrode disposed on a first diffusion region of said semiconductor substrate, a second diffusion region being bounded by said outer annular gate electrode, a portion of said outer annular gate electrode forming an active channel of said outer annular transistor and being located completely within said first diffusion region; and

at least one inner annular transistor having an inner annular gate electrode disposed on said second diffusion region, said at least one inner annular transistor being surrounded by said outer annular transistor and connected to a field oxide region completely isolated within said outer annular transistor.

2. The radiation hardened device of claim 1, further comprising an additional inner annular transistor disposed on said second diffusion region.

3. The radiation hardened device of claim 2, wherein said outer gate electrode is connected to ground, thereby isolating said at least one inner annular transistor and said additional inner annular transistor from other neighboring transistors.

4. The radiation hardened device of claim 2, wherein said at least one inner annular transistor and said additional inner annular transistor are separated from one another by a portion of said outer gate electrode extended there between.

5. The radiation hardened device of claim 2, wherein said outer annular transistor is one of a metal or polysilicon field or a metal or polysilicon gate MOS transistor.

6. The radiation hardened device of claim 1, wherein said outer annular transistor and said at least one inner annular transistor are connected to other neighboring transistors to form a logic circuit.

7. The radiation hardened device of claim 1, wherein the integrated circuit is a CMOS.

8. The radiation hardened device of claim 1, wherein the integrated circuit is a metal gate device.

9. The radiation hardened device of claim 8, wherein the metal gate device uses a grounded metal field for isolation.

10. An annular transistor, comprising:

an outer annular region of a first conductivity type on a semiconductor substrate and surrounded by a field insulator region, said outer annular region including a first contact of an integrated circuit device and having an inner edge surrounding a central area of said substrate;

an inner region of said first conductivity type on said semiconductor substrate, said inner region occupying a portion of said central area including a second contact of said integrated circuit device and separated from said outer annular region by a ring area on said substrate;

a thin insulator layer formed on the surface of said substrate in said ring area; and

a conductive layer formed on said thin insulator layer as a gate electrode of said integrated circuit device.

11. The annular transistor of claim 10, wherein a resistor is defined by positioning at least two contacts within said inner region.

12. The resistor of claim 11, wherein the resistance of the resistor is adjusted by adjusting the width of at least a portion of said outer annular region.

13. A semiconductor device, comprising:

an outer annular region of a first conductivity type on a semiconductor substrate and surrounded by a field insulator region, said outer annular region connected to a reference potential and having an inner edge surrounding a central area of said substrate;

an inner region of said first conductivity type on said semiconductor substrate, said inner region occupying a portion of said central area and separated from said outer annular region by a ring area on said substrate;

a ring insulator layer formed on the surface of said substrate in said ring area;

a conductive layer formed on said ring insulator layer and connected to said reference potential; and

said inner region having first and second electrodes forming a semiconductor component.

14. The semiconductor device of claim 13, wherein said electrical component is a resistor.

15. The semiconductor device of claim 14, wherein said resistance of the resistor is adjusted by adjusting the area of a diffusion region within outer annular region.

16. The semiconductor device of claim 13, wherein said outer annular region is in a ground state.

17. A radiation hardened integrated circuit device on a semiconductor substrate, comprising:

an outer annular region of a first conductivity type on a semiconductor substrate and surrounded by a field insulator region, said outer annular region forming a first electrode of a first integrated circuit device and having an inner edge surrounding a central area of said substrate;

an inner annular region of said first conductivity type on said semiconductor substrate, forming a second electrode of said first integrated circuit device and a first electrode of a second integrated circuit device, said inner annular region occupying a first portion of said central area and separated from said outer annular region by a first ring area on said substrate, said inner annular region having an inner edge surrounding a second portion of said central area of said substrate;

a first thin insulator layer formed on the surface of said substrate in said first ring area;

a first conductive layer formed on said first thin insulator layer as a gate electrode of said first integrated circuit device;

an inner central region of said first conductivity type on said semiconductor substrate, said inner central region occupying part of said second portion of said central area forming a second electrode of said second integrated circuit device and separated from said inner annular region by a second ring area on said substrate;

a second thin insulator layer formed on the surface of said substrate in said second ring area; and

a second conductive layer formed on said second thin insulator layer as a gate electrode of said second integrated circuit device.