Electrical mask identification of memory modules

• US 6,570,254 B1
• Filed: 05/31/2001
• Issued: 05/27/2003
• Est. Priority Date: 01/27/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Thoma, Endre P., DeForge, John B., Douse, David E., Litten, Susan M., Hedberg, Erik L., Eustis, Steven M.
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Soward, Ida M.
• Application Number:
  US09/871,087
• Time in Patent Office: 726 Days
• Field of Search: 257/209, 257/390, 257/391, 257/508, 257/758-760, 257/210-211, 257/48, 257/797
• US Class Current: 257/758
• CPC Class Codes: G03F 7/70541 Tagging, i.e. hardware or software tagging of features or components, e.g. using tagging scripts or tagging identifier codes for identification of chips, shots or wafers

Abstract

Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself.

Mask identification can be fabricated to identify the following type of mask layers: DT—deep trench; SS—surface strap; DIFF—Diffusion; NDIFF—N Diffusion; PDIFF—P Diffusion; WL—N wells; PC—polysilicon gates; BN—N diffusion Implant; BP—P diffusion Implant; C1—first contact; M1—first metal layer; C2—second contact; and, M2—second metal layer.

Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M1-C1-PC-C1-DIFF-C1-M1-C2-M2; M1-C1-PDIFF-SS-DT-SS-PDIFF-C1-M1-C2-M2; M2-C2-M1-C1-PC-C1-M1; M2-C2-M1-C1-NDIFF-WL-NDIFF-C1-M1; and, M2-C2-M1-C1-NDIFF-C1-M1-C1-PC-C1-M1. These conducting paths are electrically opened with the omission of any of the layers in the series path.

Claims

1. An apparatus for identifying the mask vintage of a semiconductor device, comprising:

a semiconductor device having a plurality of semiconductor levels of different semiconductor technologies; and

electrical devices constructed from each of said semiconductor technologies within each of said semiconductor levels, wherein said electrical devices form a mask programmable conduction path for mask identification within said semiconductor device.

2. The apparatus of claim 1 further comprising:

means for encoding said electrical devices in a binary encoded format to identify said mask vintage; and

,

means for electrically interrogating said semiconductor device for said mask vintage by reading the binary encoded electrical devices.

3. An apparatus for identifying the mask vintage of a deep trench and surface strap structure, comprising a mask programmable conduction path for mask identification within said semiconductor device, said conduction path fabricated from the technology of each of the following layers:

a first metal layer, a first contact layer, a diffusion layer, a surface strap layer, a deep trench layer, a second contact layer, and a second metal layer.

4. The apparatus of claim 3 further comprising a third contact layer and a third metal layer.

5. An apparatus for identifying the mask vintage of a polysilicon gate structure, comprising a mask programmable conduction path for mask identification within said semiconductor device, said conduction path fabricated from the technology of each of the following layers:

a first metal layer, a first contact layer, a polysilicon gate layer, a second contact layer, and a second metal layer.

6. The apparatus of claim 5 further comprising a third contact layer and a third metal layer.

8. The apparatus of claim 5 further comprising a second deeper diffusion N Well layer.

7. An apparatus for identifying the mask vintage of N Well and N Diffusion Implant structures, comprising a mask programmable conduction path for mask identification within said semiconductor device, said conduction path fabricated from the technology of each of the following layers:

a first metal layer, a first contact layer, a diffusion layer, a diffusion N Well layer, a second contact layer, and a second metal layer.

9. The apparatus of claim 7 further comprising a third contact layer and a third metal layer.

10. An apparatus for identifying the mask vintage of a substrate P-diffusion structure, comprising a mask programmable conduction path for mask identification within said semiconductor device, said conduction path fabricated from the technology of each of the following layers:

a first metal layer, a first contact layer, and a p diffusion layer.

11. An apparatus for identifying the mask vintage of a diffusion structure, first and second metal structures, first and second contact structures, comprising a mask programmable conduction path for mask identification within said semiconductor device, said conduction path fabricated from the technology of each of the following layers:

a first metal layer, a first contact layer, a polysilicon gate layer, a diffusion layer, a second contact layer, and a second metal layer.

12. The apparatus of claim 11 further comprising a third contact layer and a third metal layer.

13. An apparatus for identifying the mask vintage of a semiconductor device, comprising:

a semiconductor device having a plurality of semiconductor levels of different semiconductor technologies;

electrical devices constructed from each of said semiconductor technologies within each of said semiconductor levels, wherein said electrical devices form a mask programmable conduction path for mask identification within said semiconductor device; and

circuitry for electrical interrogation of said electrical devices to access mask identification.