Timing calibration and timing calibration verification of electronic circuit testers

• US 6,570,397 B2
• Filed: 08/07/2001
• Issued: 05/27/2003
• Est. Priority Date: 08/07/2001
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Mayder, Romi, Sugihara, Noriyuki, Tse, Andrew, Bailey, Randy L.
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): TANG, MINH NHUT
• Application Number:
  US09/923,548
• Publication Number:
  US 20030030453A1
• Time in Patent Office: 658 Days
• Field of Search: 324/754, 324/755, 324/763, 324/765, 324/73.1, 324/74, 324/158.1, 714/700, 714/726, 714/731, 714/733-734, 702/79, 702/89, 702/106, 702/118, 702/120, 702/125-126
• US Class Current: 324/750.02
• CPC Class Codes: G01R 31/319 Tester hardware, i.e. output processing circuits
• CPC Class Codes: G01R 31/3191 Calibration
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass
• CPC Class Codes: G01R 35/005 Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references G01R33/0035, G01R35/002 take precedence

Abstract

Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time. In some embodiments, test channels are connected directly to calibration board comparators to avoid the accumulated signal degradation and the signal path route errors that may result from transmitting tester channel signals through a mechanical relay selection matrix.

Claims

1. A system for calibrating an electronic circuit tester, comprising:

a substrate mountable on a test head of an electronic circuit tester, the test head having a plurality of test connectors terminating substantially in a plane;

a connector interface disposed on the substrate and comprising a plurality of test connector contact pads exposed for electrical contact with the test connectors; and

a calibration circuit supported by the substrate, electrically connected to the connector interface, and operable to connect test connectors to a source of a calibration reference signal and to one or more selected test connectors in accordance with protocols for calibrating the electronic circuit tester to the plane of the test connectors and verifying calibration of the electronic circuit tester.

2. The system of claim 1, wherein the connector interface comprises one or more calibration reference signal contact pads exposed for electrical contact with one or more test connectors electrically coupled to a source of a calibration reference signal synchronized with a clock generator of the electronic circuit tester.

3. The system of claim 2, wherein the connector interface comprises a plurality of symmetrical test channel sites distributed over an exposed surface of the substrate, each test channel site comprising a plurality of contact pads exposed for electrical contact with respective test connectors of the test head.

4. The system of claim 3, wherein the connector interface further comprises one or more reference sites each comprising one or more calibration reference signal contact pads.

5. The system of claim 4, wherein the connector interface comprises multiple symmetrical sectors each comprising a reference site and multiple test channel sites.

6. The system of claim 5, wherein the calibration circuit is configured to calibrate and verify calibration of a subset of test channels corresponding to test connectors electrically coupled to a single sector of connector interface at a time.

7. The system of claim 6, wherein the substrate is mountable on the test head at different rotational positions to enable timing calibration and timing calibration verification of different subsets of the electronic circuit tester channels.

8. The system of claim 1, wherein the calibration circuit comprises a switching network supported by the substrate, electrically coupled to the connector interface, and operable to route signals to test connectors.

9. The system of claim 8, wherein the calibration circuit further comprises a controller electrically coupled to the connector interface and the switching network, and configured to control the operation of the switching network based upon control signals received from one or more test connectors electrically coupled to the connector interface.

10. The system of claim 8, wherein the switching network comprises one or more mechanical relay selection matrices.

11. The system of claim 1, further comprising an input/output interface supported by the substrate, electrically coupled to the calibration circuit, and configured to transmit signals between the calibration circuit and external test and measurement instruments.

12. A system for calibrating an electronic circuit tester, comprising:

a substrate mountable on a test head of an electronic circuit tester, the test head having a plurality of test channel connectors coupled to test channels of the electronic circuit tester and one or more calibration reference signal connectors coupled to a source of a calibration reference signal synchronized with a clock generator of the electronic circuit tester, the test channel connectors and the one or more calibration reference signal connectors terminating substantially in a plane;

a connector interface disposed on the substrate and comprising a plurality of test channel contact pads exposed for electrical contact with the test channel connectors, and one or more calibration reference signal pads exposed for electrical contact with the calibration reference signal connectors; and

a calibration circuit supported by the substrate, electrically connected to the connector interface, and operable to connect test channel connectors to one or more calibration reference signal connectors in accordance with a protocol for calibrating the electronic circuit tester to the plane of the test head connectors.

13. The system of claim 12, wherein the calibration circuit is further operable to connect test channel connectors to one or more selected test channel connectors in accordance with a protocol for verifying calibration of the electronic circuit tester.

14. The system of claim 12, wherein the calibration circuit comprises a plurality of comparators each connected directly to a respective contact pad of the connector interface.

15. The system of claim 14, wherein the calibration circuit further comprises a strobing circuit configured to provide an indication of test channel timing error with respect to the calibration reference signal, and a selector circuit coupled between each of the comparators and the strobing circuit and configured to route signals sequentially from the comparators to the strobing circuit.

16. A system for calibrating an electronic circuit tester, comprising:

a substrate mountable on a test head of an electronic circuit tester, the test head having a plurality of test connectors terminating substantially in a plane;

a connector interface disposed on the substrate and comprising a plurality of test connector contact pads exposed for electrical contact with the test connectors; and

a calibration circuit supported by the substrate, electrically connected to the connector interface, and comprising a plurality of comparators each connected directly to a respective test connector contact pad of the connector interface.

17. The system of claim 16, wherein the calibration circuit further comprises a strobing circuit configured to provide an indication of test channel timing error with respect to a calibration reference signal, and a selector circuit coupled between each of the comparators and the strobing circuit and operable to route signals sequentially from the comparators to the strobing circuit.

18. The system of claim 16, wherein the calibration circuit is implemented as an integrated circuit.

19. An electronic circuit tester system, comprising:

a clock generator;

a calibration reference signal generator configured to generate a calibration reference signal synchronized with the test channel clock generator; and

a test head defining a plurality of test channels and having a plurality of test channel connectors coupled to the test channels and one or more calibration reference signal connectors coupled to the calibration reference signal generator, the test channel connectors and the one or more calibration reference signal connectors terminating substantially in a plane.

20. The system of claim 19, wherein the clock generator and the calibration reference signal generator are disposed on a common printed circuit board within the test head of the electronic circuit tester system.