CMOS active pixel sensor type imaging system on a chip

• US 6,570,617 B2
• Filed: 01/02/2001
• Issued: 05/27/2003
• Est. Priority Date: 01/28/1994
• Status: Expired

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Nixon, Robert, Fossum, Eric R.
• Primary Examiner(s): HO, TUAN V
• Application Number:
  US09/753,417
• Publication Number:
  US 20010002045A1
• Time in Patent Office: 875 Days
• Field of Search: 348/294, 348/295, 348/296, 348/297, 348/300, 348/301, 348/302, 348/308, 365/185.03, 365/185.33, 365/115, 250/208.1, 257/292, 257/443
• US Class Current: 348/308
• CPC Class Codes: G11C 19/282 with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14656 Overflow drain structures
• CPC Class Codes: H01L 27/14843 Interline transfer
• CPC Class Codes: H01L 27/1485 Frame transfer
• CPC Class Codes: H01L 31/02162 for filtering or shielding light, e.g. multicolour filters for photodetectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H04N 23/10 for generating image signals from different wavelengths
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A single chip camera which includes an intergrated image acquisition portion and control portion and which has double sampling/noise reduction capabilities thereon. Part of the intergrated structure reduces the noise that is picked up during imaging.

Claims

1. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors; and

a circuit, integrated on said substrate, which reduces a fixed pattern noise, wherein said signal controlling device includes a column-parallel read out device, which reads out a row of said photoreceptors at substantially the same time.

2. A camera device as in claim 1, wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor.

3. A camera device as in claim 2, wherein said readout amplifier is preferably within and/or associated with one element of the array.

4. A camera device as in claim 2, wherein said photoreceptors are photodiodes.

5. A camera device as in claim 2 wherein said photoreceptors are photogates.

6. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors;

a circuit, integrated on said substrate, which reduces a fixed pattern noise; and

a mode selector device, selecting a mode of operation of said chip, wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and a second mode of operation, different than said first mode of operation, for operation with photodiodes.

8. A camera device as in claim 6, further comprising a differencing mode which alters readout timing in such a way that the value of each pixel output represents a difference between a current frame and a previous frame.

7. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors; and

a circuit, integrated on said substrate, which reduces a fixed pattern noise,

wherein said timing circuit controls readout from said chip in a correlated double sampling mode.

9. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors; and

a circuit, integrated on said substrate, which reduces a fixed pattern noise including at least one charge storage device, sampling a level indicative of reset.

10. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors; and

a circuit, integrated on said substrate, which reduces a fixed pattern noise, including at least two charge storage devices, one controlled by said timing circuit to first sample a level indicative of reset, and another controlled by said timing circuit to second sample a level indicative of a charged device.

11. A camera device as in claim 10, further comprising a shorting element that shorts together said two charge storage devices prior to sampling said reset level.

12. A camera device as in claim 10, wherein said timing circuit allows changing an integration time for said array of photoreceptors by changing a time between said first sample and said second sample.

13. A camera device as in claim 10, wherein said timing circuit times an operation of said fixed pattern noise reduction circuit to occur during a time of the video signal which is not being displayed.

14. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors arranged in rows and columns;

a charge storage element, associated with each said column;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors;

said control portion including logic elements to control a double delta sampling, integrated on the chip, which shorts sampled signals during the readout cycle, thereby reducing column fixed pattern noise.

15. A camera device as in claim 14, wherein said signal controlling device includes a column-parallel read out device, which reads out a row of said photoreceptors at substantially the same time.

16. A camera device as in claim 14, wherein said signal controlling device includes a column selector allowing selection of a desired column for read out, and a row selector which allows selection of a desired row for readout.

17. A camera device as in claim 14, wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor.

18. A camera device as in claim 17, wherein said readout amplifier is preferably within and/or associated with one element of the array.

19. A camera device as in claim 17, wherein said photoreceptors are photodiodes.

20. A camera device as in claim 17, wherein said photoreceptors are photogates.

21. A camera device as in claim 14, further comprising a mode selector device, selecting a mode of operation of said chip.

22. A camera device as in claim 21, wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and a second mode of operation, different than said first mode of operation, for operation with photodiodes.

23. A camera device as in claim 14, wherein said timing circuit allows changing an integration time for said array of photoreceptors.

24. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors in rows and columns;

first and second charge storage elements, associated with each said column;

said control portion integrated in said substrate including a signal controlling device,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, controlling said photoreceptors to output their signals such that said first charge storage element receives the signal indicative of reset and said second charge storage element receives a signal indicative of a charged state;

said control portion including a shorting element, formed on said substrate which shorts between said first and second charge storage elements to reduce noise produced thereby.

25. A device as in claim 24, wherein said photoreceptors are controlled to read out an entire column of information at one time, wherein there are one of said first and second charge storage elements on said substrate for each element of said column, and wherein there is one of said shorting elements on said substrate for each of said columns.

26. A camera device as in claim 24, wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor.

27. A camera device as in claim 26, wherein said readout amplifier is preferably within and/or associated with one element of the array.

28. A camera device as in claim 26, wherein said photoreceptors are photodiodes.

29. A camera device as in claim 26, wherein said photoreceptors are photogates.

30. A camera device as in claim 24, wherein said timing circuit allows changing an integration time for said array of photoreceptors with changing timings of said first and second charge storage elements.

31. A method of controlling a single chip camera, comprising:

integrating, on a single substrate, an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS, said image acquisition portion integrated in said substrate including an array of photoreceptors with output nodes, and a signal controlling device, controlling said photoreceptors and a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and also integrating at least two charge storage elements on said substrate;

first, shorting together specified nodes of said two charge storage elements;

after said first shorting, sampling voltages on said charge storage elements, said voltages being related to one another.

32. A method as in claim 31, further comprising:

sampling a reset value as a first sample;

allowing said photoreceptors to accumulate charge, after resetting said output nodes;

sampling said output nodes after accumulating said charge, producing output signals indicative of a difference between said reset value and said sampled value after accumulating said charge.

33. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors and a noise reduction circuit;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals;

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors to output a plurality of outputs at a time and controlling an operation of said noise reduction circuit to occur during a time when signals are not being read from said array of photodetectors.

34. A device as in claim 33, wherein said control portion controls the timing to output a column of said array at any one time.

35. A device as in claim 33, wherein said noise reduction circuit includes a correlated double sampling circuit.