Logic process DRAM

• US 6,570,781 B1
• Filed: 06/14/2001
• Issued: 05/27/2003
• Est. Priority Date: 06/28/2000
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Lee, Winston, Sutardja, Sehat, Lee, Peter
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/881,474
• Time in Patent Office: 712 Days
• Field of Search: 365/189.01, 365/189.03, 365/189.08, 365/189.09, 365/189.02, 365/63, 365/202, 365/206, 365/210
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.

Claims

1. A semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, the DRAM unit comprising:

a plurality of bit line pairs, each bit line pair including a first bit line and a second bit line;

a plurality of activatable word lines, at most one word line being activated at a time;

a plurality of memory cells; and

a plurality of multiplexers,

the first bit line and the second bit line within each bit line pair being aligned with each other in an end-to-end arrangement; and

the first bit lines being arranged substantially in parallel with each other and consecutively adjacent to one another; and

the second bit lines being arranged substantially in parallel with each other and consecutively adjacent to one another; and

each word line being associated with either all of the first bit lines or all of the second bit lines, such that a first array is formed by the first bit lines and their associated word lines and a second array is formed by the second bit lines and their associated word lines; and

one of the plurality of memory cells being associated with every other bit line along each word line, such that for each word line, each bit line that is not associated with one of the plurality of memory cells acts as a shield between bit lines that are each associated with one of the plurality of memory cells; and

each of the plurality of multiplexers being in communication with a voltage source input and with two adjacent bit lines within one of the two arrays; and

wherein when a word line is activated, each of the plurality of multiplexers is configured to output a difference between signal levels of the two adjacent bit lines in communication with that multiplexer.

2. The device of claim 1, the array to which the activated word line belongs acting as a sense array, and the array to which the activated word line does not belong acting as a reference array, and the DRAM unit further comprising an activatable dummy word line in the first array and an activatable dummy word line in the second array, and the device being configured to detect signal levels in a common mode by activating the dummy word line in the reference array and detecting a signal level of the activated word line differentially as compared to a signal level of the activated dummy word line.

3. The device of claim 2, the DRAM unit further comprising two interconnect layers, including a first interconnect layer and a second interconnect layer, and each bit line being associated with both interconnect layers.

4. The device of claim 3, the first interconnect layer comprising a first metal layer, and the second interconnect layer comprising a second metal layer.

5. The device of claim 3, the first interconnect layer comprising a metal layer, and the second interconnect layer comprising a polysilicon layer.

6. The device of claim 3, the first interconnect layer comprising a first polysilicon layer, and the second interconnect layer comprising a second polysilicon layer.

7. The device of claim 2, the DRAM unit being manufactured using a logic process.

8. The device of claim 2, the DRAM unit being manufactured using a DRAM process.

9. A semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, the DRAM unit comprising:

a plurality of bit line pairs, each bit line pair including a first bit line and a second bit line;

a plurality of activatable word lines, at most one word line being activated at a time;

a plurality of memory cells;

a plurality of multiplexers; and

a first interconnect layer and a second interconnect layer,

the first bit line and the second bit line within each bit line pair being adjacent to each other; and

each bit line being associated with both interconnect layers; and

each word line being associated with all of the bit lines, such that an array is formed by the bit lines and the associated word lines; and

one of the plurality of memory cells being associated with every other bit line along each word line, such that for each word line, each bit line that is not associated with one of the plurality of memory cells acts as a shield between bit lines that are each associated with one of the plurality of memory cells; and

each of the plurality of multiplexers being in communication with a voltage source input and with a first bit line and a second bit line within a bit line pair; and

wherein when a word line is activated, each of the plurality of multiplexers is configured to output a difference between signal levels of the two adjacent bit lines in communication with that multiplexer.

10. The device of claim 9, the DRAM unit further comprising an activatable dummy word line, and the device being configured to detect signal levels in a common mode by activating the dummy word line and detecting a signal level of the activated word line differentially as compared to a signal level of the activated dummy word line.

11. The device of claim 10, the first interconnect layer comprising a first metal layer, and the second interconnect layer comprising a second metal layer.

12. The device of claim 11, the first bit line and the second bit line within each bit line pair being twisted at at least one point such that half of each bit line is associated with the first metal layer and half of each bit line is associated with the second metal layer.

13. The device of claim 12, the first bit line and the second bit line within at least one bit line pair being twisted at at least two points such that half of each bit line is associated with the first metal layer and half of each bit line is associated with the second metal layer.

14. The device of claim 10, the first interconnect layer comprising a metal layer, and the second interconnect layer comprising a polysilicon layer.

15. The device of claim 10, the first interconnect layer comprising a first polysilicon layer, and the second interconnect layer comprising a second polysilicon layer.

16. The device of claim 10, the DRAM unit being manufactured using a logic process.

17. The device of claim 10, the DRAM unit being manufactured using a DRAM process.

18. An apparatus for reducing noise and overall bit line capacitance in a DRAM device, comprising:

a plurality of pairs of bit line means for conducting electrical signals, each pair including a first bit line means and a second bit line means;

a plurality of activatable word line means for conducting electrical signals, at most one word line means being activated at a time;

a plurality of means for storing data; and

a plurality of means for multiplexing,

the first bit line means and the second bit line means within each bit line pair being aligned with each other in an end-to-end arrangement; and

the first bit line means being arranged substantially in parallel with each other and consecutively adjacent to one another; and

the second bit line means being arranged substantially in parallel with each other and consecutively adjacent to one another; and

each word line means being associated with either all of the first bit line means or all of the second bit line means, such that a first array is formed by the first bit line means and their associated word line means and a second array is formed by the second bit line means and their associated word line means; and

one of the plurality of means for storing data being associated with every other bit line means along each word line means, such that for each word line means, each bit line means that is not associated with one of the plurality of means for storing data acts as a shield between bit line means that are each associated with one of the plurality of means for storing data; and

each of the plurality of means for multiplexing being in communication with a voltage source input and with two adjacent bit line means within one of the two arrays; and

wherein when a word line means is activated, each of the plurality of means for multiplexing is configured to output a difference between signal levels of the two adjacent bit line means in communication with that means for multiplexing.

19. The apparatus of claim 18, the array to which the activated word line means belongs acting as a sense array, and the array to which the activated word line means does not belong acting as a reference array, and the apparatus further comprising:

an activatable dummy word line means for conducting electrical signals in the first array;

an activatable dummy word line means for conducting electrical signals in the second array; and

means for detecting signal levels in a common mode by activating the dummy word line means in the reference array and detecting a signal level of the activated word line means differentially as compared to a signal level of the activated dummy word line means.

20. The apparatus of claim 19, the device further comprising two interconnect layers, including a first interconnect layer and a second interconnect layer, and each bit line means being associated with both interconnect layers.

21. The apparatus of claim 20, the first interconnect layer comprising a first metal layer, and the second interconnect layer comprising a second metal layer.

22. The apparatus of claim 20, the first interconnect layer comprising a metal layer, and the second interconnect layer comprising a polysilicon layer.

23. The apparatus of claim 20, the first interconnect layer comprising a first polysilicon layer, and the second interconnect layer comprising a second polysilicon layer.

24. The apparatus of claim 19, the DRAM device being manufactured using a logic process.

25. The apparatus of claim 19, the DRAM device being manufactured using a DRAM process.

26. An apparatus for reducing noise and overall bit line capacitance in a DRAM device, the device comprising:

a plurality of pairs of bit line means for conducting electrical signals, each pair of bit line means including a first bit line means and a second bit line means;

a plurality of activatable word line means for conducting electrical signals, at most one word line means being activated at a time;

a plurality of means for storing data;

a plurality of means for multiplexing; and

a first interconnect layer and a second interconnect layer,

each bit line means being associated with both interconnect layers;

the first bit line means and the second bit line means within each pair of bit line means being arranged to be adjacent to each other;

each word line means being associated with all of the bit line means, such that an array is formed by the bit line means and the associated word line means;

one of the plurality of means for storing data being associated with every other bit line means along each word line means, such that for each word line means, each bit line means that is not associated with one of the plurality of means for storing data acts as a shield between bit line means that are each associated with one of the plurality of means for storing data; and

each of the plurality of means for multiplexing being in communication with a voltage source and with a first bit line means and a second bit line means within a pair of bit line means,

wherein when a word line means is activated, each of the plurality of means for multiplexing is configured to output a difference between signal levels of the two adjacent bit line means in communication with that means for multiplexing.

27. The apparatus of claim 26, the apparatus further comprising:

an activatable dummy word line means for conducting electrical signals; and

means for detecting signal levels in a common mode by activating the dummy word line means and detecting a signal level of the activated word line means differentially as compared to a signal level of the activated dummy word line means.

28. The apparatus of claim 27, the first interconnect layer comprising a first metal layer, and the second interconnect layer comprising a second metal layer.

29. The apparatus of claim 28, further comprising means for twisting the first bit line means and the second bit line means within each pair of bit line means at at least one point such that half of each bit line means is associated with the first metal layer and half of each bit line means is associated with the second metal layer.

30. The apparatus of claim 29, further comprising means for twisting the first bit line means and the second bit line means within at least one pair of bit line means at at least two points such that half of each bit line means is associated with the first metal layer and half of each bit line means is associated with the second metal layer.

31. The apparatus of claim 27, the first interconnect layer comprising a metal layer, and the second interconnect layer comprising a polysilicon layer.

32. The apparatus of claim 27, the first interconnect layer comprising a first polysilicon layer, and the second interconnect layer comprising a second polysilicon layer.

33. The apparatus of claim 27, the DRAM device being manufactured using a logic process.

34. The apparatus of claim 27, the DRAM device being manufactured using a DRAM process.

35. A method of reducing noise and overall bit line capacitance in a DRAM device, the device including a plurality of bit line pairs, a plurality of activatable word lines, a plurality of memory cells, and a plurality of multiplexers, each bit line pair including a first bit line and a second bit line, and at most one word line being activated at a time, the method comprising the steps of:

aligning the first bit line and the second bit line within each bit line pair in an end-to-end arrangement;

arranging the first bit lines substantially in parallel with each other and consecutively adjacent to one another;

arranging the second bit lines substantially in parallel with each other and consecutively adjacent to one another;

associating each word line with either all of the first bit line means or all of the second bit line means, such that a first array is formed by the first bit lines and their associated word lines and a second array is formed by the second bit lines and their associated word lines;

associating one of the plurality of memory cells with every other bit line along each word line, such that for each word line, each bit line that is not associated with one of the plurality of memory cells acts as a shield between bit lines that are each associated with one of the plurality of memory cells;

bringing each multiplexer of the plurality of multiplexers into communication with a voltage source input and with two adjacent bit lines within one of the two arrays; and

configuring each multiplexer to output a difference between signal levels of the two adjacent bit lines in communication with that multiplexer when a word line is activated.

36. The method of claim 35, the array to which the activated word line belongs acting as a sense array, and the array to which the activated word line does not belong acting as a reference array, and the device further including an activatable dummy word line in the first array and an activatable dummy word line in the second array, and the method further comprising the step of detecting signal levels in a common mode by activating the dummy word line in the reference array and detecting a signal level of the activated word line differentially as compared to a signal level of the activated dummy word line.

37. The method of claim 36, the device further comprising two interconnect layers, including a first interconnect layer and a second interconnect layer, and the method further comprising the step of associating each bit line with both interconnect layers.

38. The method of claim 37, the first interconnect layer comprising a first metal layer, and the second interconnect layer comprising a second metal layer.

39. The method of claim 37, the first interconnect layer comprising a metal layer, and the second interconnect layer comprising a polysilicon layer.

40. The method of claim 37, the first interconnect layer comprising a first polysilicon layer, and the second interconnect layer comprising a second polysilicon layer.

41. The method of claim 36, the DRAM device being manufactured using a logic process.

42. The method of claim 36, the DRAM device being manufactured using a DRAM process.

43. A method of reducing noise and overall bit line capacitance in a DRAM device, the device including a plurality of bit line pairs, a plurality of activatable word lines, a plurality of memory cells, a plurality of multiplexers, and a first interconnect layer and a second interconnect layer, each bit line pair including a first bit line and a second bit line, and at most one word line being activated at a time, the method comprising the steps of:

associating each bit line with both interconnect layers;

arranging the first bit line and the second bit line within each bit line pair to be adjacent to each other;

associating each word line with all of the bit lines, such that an array is formed by the bit lines and the associated word lines;

associating one of the plurality of memory cells with every other bit line along each word line, such that for each word line, each bit line that is not associated with one of the plurality of memory cells acts as a shield between bit lines that are each associated with one of the plurality of memory cells;

bringing each multiplexer of the plurality of multiplexers into communication with a voltage source and with a first bit line and a second bit line within a bit line pair; and

configuring each multiplexer to output a difference between signal levels of the two adjacent bit lines in communication with that multiplexer when a word line is activated.

44. The method of claim 43, the device further including an activatable dummy word line, and the method further comprising the step of detecting signal levels in a common mode by activating the dummy word line and detecting a signal level of the activated word line differentially as compared to a signal level of the activated dummy word line.

45. The method of claim 44, the first interconnect layer comprising a first metal layer, and the second interconnect layer comprising a second metal layer.

46. The method of claim 45, further comprising the step of twisting the first bit line and the second bit line within each bit line pair at at least one point such that half of each bit line is associated with the first metal layer and half of each bit line is associated with the second metal layer.

47. The method of claim 46, further comprising the step of twisting the first bit line and the second bit line within at least one bit line pair at at least two points such that half of each bit line is associated with the first metal layer and half of each bit line is associated with the second metal layer.

48. The method of claim 44, the first interconnect layer comprising a metal layer, and the second interconnect layer comprising a polysilicon layer.

49. The method of claim 44, the first interconnect layer comprising a first polysilicon layer, and the second interconnect layer comprising a second polysilicon layer.

50. The method of claim 44, the DRAM device being manufactured using a logic process.

51. The method of claim 44, the DRAM device being manufactured using a DRAM process.