Highly compact EPROM and flash EEPROM devices

• US 6,570,790 B1
• Filed: 11/17/1993
• Issued: 05/27/2003
• Est. Priority Date: 06/08/1988
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/154,162
• Time in Patent Office: 3,478 Days
• Field of Search: 365/182, 365/185, 365/189.01, 365/185.01, 365/230.01, 365/230.03, 365/185.28, 365/185.26, 365/185.18, 365/185.19, 365/185.2, 365/185.29
• US Class Current: 365/185.29
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 438/964 : Roughened surface

Abstract

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. A nonvolatile memory system, comprising:

a plurality of nonvolatile memory blocks each having a plurality of memory cells, at least one of said plurality of nonvolatile memory blocks containing no data and not having been previously accessed;

at least one counter means for counting a number of erase/write cycles that each of the plurality of nonvolatile memory blocks experience; and

means, coupled to said at least one counter means, for reallocating data contained in a first memory block to said at least one memory block when the at least one counter means counts, for said first memory block, up to a predetermined value.

2. The system according to claim 1, wherein said predetermined value represents a predetermined endurance limit of each of said nonvolatile memory cell blocks.

3. A method for counting a number of erase/write cycles of a nonvolatile memory system including a plurality of nonvolatile memory blocks, at least one of said plurality of nonvolatile memory blocks containing no data and not having been previously accessed, the method comprising:

counting a number of erase/write cycles that the plurality of nonvolatile memory blocks experience, respectively; and

reallocating data contained in a first memory block to said at least one memory block when the counted number of erase/write cycles of said first memory block is equal to a predetermined value.

4. The method according to claim 3, wherein said predetermined value represents a predetermined endurance limit of nonvolatile memory cells of each of said memory blocks.

5. The method according to claim 3, further comprising the steps of determining any errors in the non-volatile memory system, and incrementing the counted number of erase/write cycles by one if no errors are determined.

6. A method of operating a plurality of blocks of nonvolatile, electrically erasable and programmable memory cells on a semiconductor chip, wherein the memory cells within the individual blocks are simultaneously erasable, comprising the steps of:

subjecting cells within the plurality of memory blocks to a number of program/erase cycles, wherein at least one block of memory cells is erased at a time and memory cells within an erased block are programmed by verifying their programmed states with reference levels that correspond to data being stored,

maintaining separate counts of a number of program/erase cycles experienced by individual ones of said memory blocks,

providing a redundant memory block, and

replacing one of said plurality of memory blocks with said redundant memory block when the counted number of program/erase cycles of said one memory block reaches a set number.

7. The method according to claim 6, wherein said set number represents a predetermined limit of a number of program/erase cycles that the memory cells of the individual memory blocks can withstand.

8. The method according to claim 7 wherein the step of maintaining the experience counts includes storing individual counts within the individual blocks to which the counts pertain.

9. The method according to claim 6 wherein the step of maintaining the experience counts includes storing individual counts within the individual blocks to which the counts pertain.

10. The method according to either of claims 6 or 7, additionally comprising programming individual ones of the memory cells into one of exactly two states in order to store exactly one bit of data per memory cell.

11. The method according to either of claims 6 or 7, additionally comprising programming individual ones of the memory cells into one of more than two states in order to store more than one bit of data per memory cell.

12. A method of of operating a flash semiconductor memory including an array of non-volatile memory cells formed on a semiconductor chip, wherein the memory cells contain elements that store a level of charge indicative of data being stored in the memory cells, comprising:

erasing memory cells by simultaneously applying erase voltages to at least one block of memory cells at a time,

programming data into the array by applying programming voltages to at least one addressed cell at a time within an erased memory cell block, including verifying the programmed state with at least one program reference level,

reading data from the array by applying reading voltages to at least one addressed programmed memory cell at a time, including comparing a read state with at least one read reference level,

subjecting cells within individual ones of the plurality of memory blocks to a number of successive erasing and programming operations,

maintaining indications of a number of erase operations experienced by individual ones of said memory cell blocks,

providing a redundant memory cell block, and

replacing one of said plurality of memory blocks with said redundant memory block when the indication of the number of erase operations of said one memory block reaches a set indication.

13. The method according to claim 12, wherein said set indication represents a predetermined limit of a number of erase operations that the memory cells of the individual memory blocks can withstand.

14. The method according to either of claims 12 or 13 wherein maintaining the indications of a number of erase operations experienced by the memory blocks includes storing individual indications within the individual blocks to which the indications pertain.

15. The method according to either of claims 12 or 13 wherein maintaining the indications of a number of erase operations experienced by the memory blocks includes storing individual indications outside of the individual blocks to which the indications pertain.

16. The method according to either of claims 12 or 13, wherein the programming operations include programming individual ones of the storage elements of erased blocks into one of more than two states in order to store more than one bit of data per storage element.

17. A method of operating a flash semiconductor memory including an array of non-volatile memory cells formed on a semiconductor chip with charge storage elements and organized into plurality of blocks of said cells, wherein the memory cells within individual ones of said blocks are simultaneously erased together, comprising:

subjecting cells within the plurality of memory blocks to a number of successive erase and programming operations,

wherein the programming operations include programming individual ones of the storage elements of erased blocks into more than two states in order to store more than one bit of data per storage element,

maintaining indications of a number of erase operations experienced by individual ones of said memory cell blocks, said indications being maintained in the individual blocks to which the indications pertain,

providing a redundant memory cell block, and

replacing one of said plurality of memory blocks with said redundant memory block when the indication of the number of erase operations of said one memory block reaches a set indication.

18. The method according to claim 17, wherein said set indication represents a predetermined limit of a number of erase operations that the memory cells of the individual memory blocks can withstand.

19. A method of operating a flash semiconductor memory including an array of non-volatile memory cells formed on a semiconductor chip with charge storage elements and organized into plurality of blocks of said cells, wherein the memory cells within individual ones of said blocks are simultaneously erased together, comprising:

subjecting cells within the plurality of memory blocks to a number of successive erase and programming operations,

wherein the programming operations include programming individual ones of the storage elements of erased blocks into more than two states in order to store more than one bit of data per storage element,

maintaining indications of a number of erase operations experienced by individual ones of said memory cell blocks, said indications being maintained outside of the individual blocks to which the indications pertain,

providing a redundant memory cell block, and

replacing one of said plurality of memory blocks with said redundant memory block when the indication of the number of erase operations of said one memory block reaches a set indication.

20. The method according to claim 19, wherein said set indication represents a predetermined limit of a number of erase operations that the memory cells of the individual memory blocks can withstand.

21. A method of operating a flash semiconductor memory including an array of non-volatile memory cells formed on a semiconductor chip with charge storage elements and organized into a plurality of blocks of said cells, comprising:

simultaneously erasing the memory cells within at least one of said blocks to an erased state by applying erase voltages to the memory cells of said at least one of said blocks,

thereafter programming incoming data into addressed ones of the charge storage elements within the erased block by designating at least two charge storage states in order to store at least one bit of the incoming data per charge storage element, including;

applying programming voltages in a pulse to at least one addressed memory cell to drive the programmed state of a charge storage element of the addressed cell from the erased state toward one of said at least two charge storage states corresponding to the incoming data to be stored therein,

thereafter monitoring the state of the charge storage element of said at least one addressed memory cell, and

continuing to apply programming voltage pulses to said at least one addressed memory cell and monitoring the state of the charge storage element until said at least one addressed cell has reached said one of said at least two charge storage states corresponding to the incoming data to be stored therein,

subjecting cells within the plurality of memory blocks to a number of successive erase and programming operations,

maintaining indications of a number of erase operations experienced by individual ones of said memory cell blocks,

providing a redundant memory cell block, and

replacing one of said plurality of memory blocks with said redundant memory block when the indication of the number of erase operations of said one memory block reaches a set indication.

22. The method according to claim 21, wherein said set indication represents a predetermined limit of a number of erase operations that the memory cells of the individual memory blocks can withstand.

23. The method according to claim 21, wherein maintaining the indications of a number of erase operations experienced by the memory blocks includes storing individual indications within the individual blocks to which the indications pertain.

24. The method according to claim 21, wherein maintaining the indications of a number of erase operations experienced by the memory blocks includes storing individual indications outside of the individual blocks to which the indications pertain.

25. The method according to claim 21, wherein maintaining indications of the number of erase operations includes maintaining numerical counts of the number of erase operations.

26. The method according to claim 21, additionally comprising reading the states of programmed memory cell charge storage elements with the assistance of an error detection and correction scheme in order to tolerate a number of memory cell read failures.

27. The method according to claim 21, additionally comprising reading the states of programmed memory cell charge storage elements by applying reading voltages to at least one programmed memory cell and simultaneously comparing a resulting level of an electrical parameter with two or more reference levels of said parameter.

28. A method of operating a flash semiconductor memory, comprising:

utilizing an array of non-volatile memory cells formed on a semiconductor substrate in rows and columns with adjacent memory cells along rows sharing common source and drain regions between them and including charge storage elements positioned over channel regions between adjacent source and drain regions, said array being organized into a plurality of blocks of said cells, wherein the memory cells within individual ones of said blocks are simultaneously erased,

subjecting cells within the plurality of memory blocks to a number of successive erase and programming operations,

maintaining indications of a number of erase operations experienced by individual ones of said memory cell blocks,

providing a redundant memory cell block, and

replacing one of said plurality of memory blocks with said redundant memory block when the indication of the number of erase operations of said one memory block reaches a set indication.

29. The method according to claim 28, wherein the array being utilized includes its individual memory cells with their charge storage elements extending over a first portion of and charge coupled with a substrate channel region between adjacent source and drain regions and a gate extending over and charge coupled with a second portion of the substrate channel region.

30. The method according to claim 28, wherein said set indication represents a predetermined limit of a number of erase operations that the memory cells of the individual memory blocks can withstand.

31. The method according to claim 28 wherein maintaining the indications of a number of erase operations experienced by the memory blocks includes storing individual indications within, the individual blocks to which the indications pertain.

32. The method according to claim 28 wherein maintaining the indications of a number of erase operations experienced by the memory blocks includes storing individual indications outside of the individual blocks to which the indications pertain.

33. The method according to either of claims 28 or 29, wherein the programming operations include programming individual ones of the storage elements of erased blocks into one of exactly two states in order to store exactly one bit of data per storage element.

34. The method according to either of claims 28 or 29, wherein the programming operations include programming individual ones of the storage elements of erased blocks into one of more than two states in order to store more than two bits of data per storage element.

35. A method of operating a flash semiconductor memory, comprising:

utilizing an array of non-volatile memory cells formed on a semiconductor substrate in rows and columns and individually including a charge storage element extending over a first portion of and charge coupled with a substrate channel region between adjacent source and drain regions and a gate extending over and charge coupled with a second portion of the substrate channel region, said array being organized into a plurality of blocks of said cells wherein the memory cells within individual ones of said blocks are simultaneously erased,

subjecting cells within the plurality of memory blocks to a number of successive erase and programming operations,

maintaining indications of-a number of erase operations experienced by individual ones of said memory cell blocks,

providing a redundant memory cell block, and

replacing one of said plurality of memory blocks with said redundant memory block when the indication of the number of erase operations of said one memory block reaches a set indication.

36. The method according to claim 35, wherein the programming operations include programming individual ones of the storage elements of erased blocks into one of more than two states in order to store more than two bits of data per storage element.

37. The method according to claim 36, wherein the programming operations further include:

applying programming voltages to at least one addressed memory cell to drive the programmed state of a storage element of the addressed cell toward one of said more than two charge storage states corresponding to the incoming data to be stored therein,

thereafter monitoring the state of the storage element of said at least one addressed memory cell,

thereafter comparing the monitored state of the storage element of said at least one addressed memory cell with the state corresponding to the incoming data to be stored therein, and

continuing to apply programming voltages to said at least one addressed memory cell and comparing its monitored state until said at least one addressed cell has reached its said state corresponding to the incoming data to be stored therein.