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Antifuse memory cell and antifuse memory cell array

  • US 6,570,805 B2
  • Filed: 12/20/2000
  • Issued: 05/27/2003
  • Est. Priority Date: 12/20/2000
  • Status: Expired due to Fees
First Claim
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1. The programmable circuit structure comprising;

  • a first circuit node and a second circuit node programmably coupled by a pass transistor having a control gate; and

    an antifuse memory cell coupled to said control gate wherein said antifuse memory cell comprises;

    a first antifuse having a first electrode coupled to said control gate through an output node and a second electrode coupled to a pull-up voltage source;

    a second antifuse having a first electrode coupled to said control gate through said output node and a second electrode coupled to a pull-down voltage source.

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