Integrated circuit device which outputs data after a latency period transpires

• US 6,570,814 B2
• Filed: 06/28/2001
• Issued: 05/27/2003
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/893,836
• Publication Number:
  US 20020001253A1
• Time in Patent Office: 698 Days
• Field of Search: 365/189.05, 365/194, 365/233, 365/233.5
• US Class Current: 365/233.1
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit device which includes an array of dynamic memory cells. The integrated circuit device comprises an input receiver to sample an operation code synchronously with respect to a transition of a clock signal, the operation code indicating a read operation. The integrated circuit device also comprises an output driver to output data in response to the operation code, wherein the data is output after a number of clock cycles of the clock signal transpire.

Claims

1. A method of operation of a synchronous dynamic random access memory device, wherein the memory device includes an array of dynamic memory cells, the method of operation of the memory device comprises:

sampling an operation code synchronously with request to a transition of an external clock signal, wherein the operation code specifies a read operation to the memory device; and

outputting data, in response to the operation code, synchronously with respect to the external clock signal, wherein the data is output after a programmed latency period transpires.

2. The method of claim 1 wherein the programmed latency period is representative of a plurality of clock cycles of the external clock signals.

3. The method of claim 1 wherein, after programming, the programmed latency period is permanent.

4. The method of claim 1 wherein the programmed latency period is represented by a value which is stored in a register disposed on the memory device.

5. The method of claim 1 further including generating an internal clock signal using a delay lock loop circuit and the external clock signal, wherein the data is output synchronously with respect to the internal clock signal.

6. The method of claim 1 wherein the programmed latency period is programmed by hard-wiring.

7. The method of claim 1 wherein the operation code includes precharge information that specifies precharging a plurality of sense amplifiers used to access the data from the array of dynamic memory cells, the method further including precharging the plurality of sense amplifiers automatically following the access of the data.

8. The method of claim 1 further including sampling address information synchronously with respect to the external clock signal.

9. The method of claim 1 wherein the address information and the operation code are included in a read request packet.

10. The method of claim 9 wherein:

sampling the operation code includes sampling the operation code synchronously with respect to a rising edge transition of the external clock signal; and

sampling the address information includes sampling the address information synchronously with respect to a falling edge transition of the external clock signal.

11. The method of claim 1 wherein outputting data further includes:

outputting a first portion of the data synchronously with respect to a rising edge transition of the external clock signal; and

outputting a second position of the data synchronously with respect to a falling edge transition of the external clock signal.

12. The method of claim 1 further including receiving block size information, wherein the block size information defines an amount of data to be output by the memory device in response to the operation code.

13. A synchronous dynamic random access memory device having an array of dynamic memory cells, the memory device comprises:

at least one input receiver to sample an operation code synchronously with respect to a transition of an external clock signal, wherein the operation code specifies a read operation to the memory device; and

an output driver to output in response to the operation code, wherein the data is output synchronously with respect to the external clock signal and after a programmed latency period transpires, wherein the programmed latency period corresponds to a number of clock cycles of the external clock signal.

14. The memory device of claim 13 wherein, after programming, the programmed latency period is permanent.

15. The memory device of claim 13 further including a register to store a value which is representative of the programmed latency period.

16. The memory device of claim 13 further including a multiplexer coupled to the output driver, wherein:

the multiplexer provides a first portion of the data to the output driver in response to a rising edge transition of the external clock signal; and

the multiplexer provides a second portion of the data to the output driver in response to a falling edge transition of the external clock signal.

17. The memory device of claim 13 wherein the output driver is coupled to an external bus, wherein the external bus includes a plurality of signal lines.

18. The memory device of claim 17 wherein the data and the operation code are multiplexed over the plurality of signal lines.

19. The memory device of claim 18 wherein the operation code is included in a request packet.

20. The memory device of claim 13 further including a delay lock loop to generate an internal signal using the external clock signal, wherein the output driver outputs data in response to the internal clock signal.

21. The memory device of claim 13 wherein:

the output driver outputs a first portion of the data synchronously with respect to a rising edge transition of the external clock signal; and

the output driver outputs a second portion of the data synchronously with respect to a falling edge transition of the external clock signal.

22. The memory device of claim 13 wherein the programmed latency period is programmed by hard-wiring.

23. The memory device of claim 13 wherein the operation code includes precharge information, and wherein the memory device further includes a plurality of sense amplifiers to access the data from the array of dynamic memory cells, wherein, in response to the precharge information, the sense amplifiers are automatically precharged after accessing the data.

24. An integrated circuit device having an array of dynamic memory cells, the integrated circuit device comprises:

at least one input receiver to sample an operation code synchronously with respect to a transition of a clock signal; and

an output driver to output data in response to the operation code, wherein the data is output after a programmed number of clock cycles of the clock signal transpire.

25. The integrated circuit device of claim 24 wherein, after programming, the programmed number of clock cycles of the clock signal is permanent.

26. The integrated circuit device of claim 25 wherein the programmed number of clock cycles of the clock signal is hard-wired.

27. The integrated circuit device of claim 24 wherein the integrated circuit device is a synchronous memory device.

28. The integrated circuit device of claim 24 wherein the operation code includes precharge information, and wherein the integrated circuit device further includes a plurality of sense amplifiers to access the data from the array of dynamic memory cells, wherein, in response to the precharge information, the sense amplifiers are automatically precharging after accessing the data.

29. The integrated circuit device of claim 24 further including a register to store a value which is representative of the programmed number of clock cycles of the clock signal.

30. The integrated circuit device of claim 24 wherein:

the output driver outputs a first portion of the data synchronously with respect to a rising edge transition of the clock signal; and

the output driver outputs a second portion of the data synchronously with respect to a falling edge transition of the clock signal.

31. The integrated circuit device of claim 30, further including a multiplexer coupled to the output driver, wherein:

the multiplexer provides the first portion of the data to the output driver in response to the rising edge transition of the clock signal; and

the multiplexer provides the second portion of the data to the output driver in response to the falling edge transition of the clock signal.

32. The integrated circuit device of claim 24, further including a delay lock loop, coupled to the output driver, to generate an internal clock signal using the clock signal, wherein the output driver outputs the data in response to the internal clock signal.

33. The integrated circuit device of claim 24 wherein the output driver outputs the data onto a bus that includes a plurality of signal lines.

34. The integrated circuit device of claim 24 wherein the at least one input receiver samples address information on a rising edge transition of the clock signal.

35. A method of controlling a synchronous dynamic random access memory device by a memory controller, wherein the memory device includes an array of dynamic memory cells, the method of controlling the memory device comprises:

issuing the operation code to the memory device synchronously with respect to an external clock signal, the operation code specifying a read operation to the memory device; and

sampling data, which is output from the memory device, after a latency period transpires, wherein the memory device outputs the data in response to the operation code and after the latency period transpires.

36. The method of claim 35 wherein the latency period corresponds to a number of clock cycles of the external clock signal.

37. The method of claim 35 further including providing address information to the memory device.

38. The method of claim 35 wherein the operation code includes precharge information that specifies that the memory device precharge a plurality of sense amplifiers used to access the data from the array of dynamic memory cells, wherein the memory device automatically precharges the sense amplifiers following the access of the data.

39. The method of claim 35 further including providing block size information to the memory device, wherein the block size information defines an amount of data to be output by the memory device in response to the operation code.

40. The method of claim 39 wherein the operation code, address information, and the block size information are included in a packet.

41. The method of claim 40 wherein the operation code, the address information, and the block size information are included in the same packet.

42. The method of claim 35 wherein the operation code is issued onto an external bus, wherein the external bus includes a plurality of signal lines.

43. The method of claim 42 wherein the plurality of signal lines carries the operation code, address information and the data.