Circuit and method for reducing memory idle cycles

• US 6,570,816 B2
• Filed: 10/21/2002
• Issued: 05/27/2003
• Est. Priority Date: 08/21/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pawlowski, Joseph T., Wilford, John R.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US10/274,773
• Publication Number:
  US 20030035339A1
• Time in Patent Office: 218 Days
• Field of Search: 365/233, 365/230.02, 365/230.03, 365/230.08, 365/189.04, 365/189.02, 365/189.05
• US Class Current: 365/189.02
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Abstract

An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM'"'"'s array reads out the full N bits simultaneously, the array'"'"'s address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array'"'"'s address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.

Claims

1. A method for retrieving a plurality of sequentially stored data bits, comprising:

latching an address of a first one of said plurality of sequentially stored data bits;

simultaneously addressing a plurality of storage elements having said plurality of sequentially stored data bits stored therein;

simultaneously sensing and latching said plurality of sequentially stored data bits from said plurality of storage elements;

outputting said first one of said plurality of sequentially stored data bits;

generating burst addresses for at least a portion of others of said plurality of sequentially stored data bits; and

for each of said burst addresses, outputting others of said plurality of sequentially stored data bits.

2. A method for retrieving a plurality of data bits, comprising:

selecting a row of addressable data storage elements from an external address;

simultaneously sensing and temporarily latching said plurality of data bits stored in said row;

according to said external address, outputting a portion of said temporarily latched plurality of data bits;

generating one or more internal burst addresses from said external address; and

for each of said one or more internal burst addresses, outputting another portion of said temporarily latched plurality of data bits in accordance with said each of said one or more internal burst addresses.

3. The method of claim 2, wherein said addressable data storage elements have a burst length of X, and wherein said outputting a portion of said temporarily latched plurality of data bits comprises selecting an equal number of said plurality of data bits for each of said outputting steps and further where X comprises a nonzero positive integer.

4. The method of claim 2, wherein said addressable data storage elements have a burst length of X, where X comprises a nonzero positive integer, and wherein the act of generating one or more internal burst addresses comprises generating X-1 internal burst addresses.

5. A method for storing a plurality of data bits, comprising:

receiving an externally supplied address corresponding to a storage location for a first portion of said plurality of data bits of sequential portions;

generating one or more internal burst addresses from said externally supplied address;

for said externally supplied address and for each internal burst address generated, temporarily storing one of said sequential portions of said plurality of data bits; and

simultaneously writing said temporarily stored one of said sequential portions of said plurality of data bits into a row of addressable data storage elements identified by said externally supplied address.

6. The method of claim 5, wherein said addressable data storage elements have a burst length of X, where X comprises a nonzero positive integer, and wherein receiving said plurality of data bits comprises receiving said plurality of data bits in sequential portions having an equal number of said plurality of data bits.

7. The method of claim 5, wherein said addressable data storage elements have a burst length of X, where X comprises a nonzero positive integer, and wherein temporarily storing one of said sequential portions of said plurality of data bits comprises temporarily storing one of said sequential portions of said plurality of data bits in latched write drivers.

8. A memory storage circuit for burst transfer of a plurality of sequential data portions, comprising:

a memory array configured to store a plurality of sequential data portions;

storage circuitry coupled to said memory array configured for temporarily storing said plurality of sequential data portions;

buffer circuitry for buffering said plurality of sequential data portions;

multiplexing circuitry coupled between said storage circuitry and said buffer circuitry for sequentially transferring said plurality of sequential data portions between said storage circuitry and said buffer circuitry; and

circuitry coupled to said storage circuitry for directing said storage circuitry to simultaneously transfer said plurality of sequential data portions of said memory array and said storage circuitry.

9. The memory storage circuit, as recited in claim 8, wherein said memory array comprises a sub-array.

10. The memory storage circuit, as recited in claim 8, wherein said storage circuitry comprises latched sense amplifiers and latched write drivers.

11. The memory storage circuit, as recited in claim 8, wherein said buffer circuitry comprises at least one of input buffer circuitry and output buffer circuitry.