Receive filtering for communication interface

• US 6,570,884 B1
• Filed: 11/05/1999
• Issued: 05/27/2003
• Est. Priority Date: 11/05/1999
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Cross, Patricia, Connery, Glenn William
• Primary Examiner(s): Vanderpuye, Ken
• Assistant Examiner(s): Phunkulh, Bob A.
• Application Number:
  US09/434,253
• Time in Patent Office: 1,299 Days
• Field of Search: 370/389, 370/419, 370/422, 370/423, 370/428, 370/429, 370/395, 370/230, 370/232, 370/235, 370/236, 370/400, 370/401, 709/250, 713/153, 713/154
• US Class Current: 370/419
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 69/12 Protocol engines

Abstract

An interface card for a network or other communication channel, with limited intelligence, is implemented using a relatively slower, and lower cost embedded processor, supported by dedicated hardware logic for the purposes of intercepting certain packets being received via the network or communication channel. The interface comprises the first port on which incoming data is received at the data transfer rate of the network, a buffer coupled to the port that stores received packets, and a second port coupled with the buffer through which transfer of packets to the host is executed. Packet filters are coupled to the first port which identifies packets being stored in the buffer that have one of the plurality of variant formats. A processor is coupled with the buffer as well, and is responsive to the packet filter to process identified packets in the buffer. The pattern match logic includes mask logic circuits, circuits to generate a hash in response to bytes selected by the mask, and a comparator which compares the output of the hash logic with an expected hash. If a match is detected, then the processor is signaled that the packet being received is, or may be, suitable for processing on the network interface card. The mask logic uses the mask modifier in response to the packet format, so that variations of a particular format can be handled with a single set of pattern match logic circuits.

Claims

1. An interface in which packets are received having a plurality of variant formats, and transferred to a host system, comprising:

a first port on which incoming data is received at a data transfer rate;

a buffer, coupled to the first port, storing received packets;

a second port, coupled with the buffer, through which transfer of packets to the host is executed;

a packet filter, coupled to the first port, which identifies packets being stored in the buffer having one of the plurality of variant formats;

first logic coupled with the buffer and the second port, to transfer packets from the buffer to the second port; and

second logic coupled with the buffer, and responsive to the packet filter to read and process data in the identified packets from the buffer, and to produce a data value dependent on contents of the packet prior to transfer of the identified packets to the second port by the first logic.

2. The interface of claim 1, wherein the second logic comprises a general purpose processor module.

3. The interface of claim 2, wherein the buffer includes memory for a plurality of packets having a typical size.

4. The interface of claim 1, wherein the buffer comprises a First-In-First-Out buffer.

5. The interface of claim 1, wherein the first port comprises a medium access control unit configured for a network having a data rate of 100 Mbits/second or higher.

6. The interface of claim 2, wherein the processor executes instructions at a rate of 50 million per second or less.

7. The interface of claim 2, wherein the first port, buffer, second port, packet filter, first logic and processor comprise components of a single integrated circuit.

8. The interface of claim 1, wherein the packet filter comprises:

mask logic circuits;

hash logic to generate a hash in response to the packet and the mask logic circuits; and

compare logic to compare the hash generated with an expected hash for one of the plurality of variant formats.

9. The interface of claim 1, wherein the packet filter comprises:

mask logic circuits, having a mask and a mask modifier logic to modify the mask using the mask modifier in response to the packet;

hash logic to generate a hash in response to the packet and the mask; and

compare logic to compare the hash generated with an expected hash for one of the plurality of variant formats.

10. The interface of claim 1, wherein the packet filter comprises a plurality of match logic circuits, each match logic circuit in the plurality comprising:

mask logic circuits storing a mask identifying selected bytes within a packet of a particular format in the plurality of variant formats;

hash logic to generate a hash in response to the selected bytes; and

compare logic to compare the hash generated with an expected hash for the particular format.

11. The interface of claim 1, wherein the second logic to process the packet comprises a routine to discover an internet protocol IP address of the host system.

12. The interface of claim 1, wherein the second logic to process the packet comprises a routine to issue a reboot command to the host system.

13. The interface of claim 1, including third logic which signals the second logic to process the data after at least part of the identified packet is stored in the buffer.

14. The interface of claim 1, including third logic which signals the second logic to process the data after the identified packet is stored in the buffer.

15. The interface of claim 1, including third logic which, after at least part of the identified packet is stored in the buffer, stops the transferring of packets to the host by the first logic, signals the second logic to process the data, and re-starts the transferring of packets to the host by the first logic in response to a signal from the second logic.

16. An interface in which packets are received having a plurality of variant formats, and transferred to a host system, comprising:

a first port on which incoming data is received at a data transfer rate;

a buffer, coupled to the first port, storing received packets;

a second port, coupled with the buffer, through which transfer of packets to the host is executed;

a packet filter, coupled to the first port, which identifies packets being stored in the buffer having one of the plurality of variant formats; and

first logic coupled with the buffer, and responsive to the packet filter to process data in the identified packets; and

second logic to manage the buffer which associates a control field with packets being stored in the buffer, and wherein the packet filter sets a variable in the control field to indicate whether the packet has one of the plurality of variant formats.

17. The interface of claim 16, including third logic which signals the first logic to process data when the variable indicates that the packet has one of the plurality of variant formats.

18. The interface of claim 16, including third logic which signals the first logic to process the data after at least part of the packet is stored in the buffer, when the variable indicates that the packet has one of the plurality of variant formats.

19. The interface of claim 16, including third logic which signals the first logic to process the data after the packet is stored in the buffer, when the variable indicates that the packet has one of the plurality of variant formats.

20. The interface of claim 16, including third logic which, after at least part of the identified packet is stored in the buffer, and when the variable indicates that the packet has one of the plurality of variant formats, stops the transferring of packets to the host, and signals the first logic to process the data, and re-starts the transferring of packets to the host in response to a signal resulting from processing the data in the first logic.

21. An interface to a network in which packets are received having a plurality of variant formats, and transferred to a host system, comprising:

a medium access control (MAC) unit on which incoming data is received at a data transfer rate;

a buffer, coupled to the MAC unit, storing received packets;

a port, coupled with the buffer, through which transfer of packets to the host is executed;

a packet filter, coupled to the MAC unit, which identifies packets being stored in the buffer having one of the plurality of variant formats; and

a processor coupled with the buffer, and responsive to the packet filter that executes instructions to read data in the identified packets from the buffer and process the read data to produce a data value, prior to transfer of the identified packets from the buffer to the host.

22. The interface of claim 21, wherein the processing of identified packets by the processor takes a typical amount of processing time for a typical packet, and the buffer stores a typical packet in an amount of time less than the typical amount of processing time.

23. The interface of claim 21, wherein the buffer includes memory for a plurality of packets having a typical size.

24. The interface of claim 21, wherein the buffer comprises a First-In-First-Out buffer.

25. The interface of claim 21, wherein the MAC unit is configured for a network having a data rate of 100 Mbits/second or higher.

26. The interface of claim 21, wherein the processor executes instructions at a rate of 50 million per second or less.

27. The interface of claim 21, wherein the MAC unit, buffer, port, packet filter and processor comprise components of a single integrated circuit.

28. The interface of claim 21, including logic to manage the buffer which associates a control field with packets being stored in the buffer, and wherein the packet filter sets a variable in the control field to indicate whether the packet has one of the plurality of valiant formats.

29. The interface of claim 21, wherein the processor comprises a routine to discover an internet protocol IP address of the host system.

30. The interface of claim 21, wherein the processor comprises a routine to issue a reboot command to the host system.

31. The interface of claim 21, wherein the packet filter comprises:

mask logic circuits;

hash logic to generate a hash in response to the packet and the mask logic; and

compare logic to compare the hash generated with an expected hash for one of the plurality of variant formats.

32. The interface of claim 21, wherein the packet filter comprises:

mask logic circuits, having a mask and a mask modifier logic to modify the mask using the mask modifier in response to the packet;

hash logic to generate a hash in response to the packet and the mask; and

compare logic to compare the hash generated with an expected hash for one of the plurality of variant formats.

33. The interface of claim 21, wherein the packet filter comprises a plurality of match logic circuits, each match logic circuit in the plurality comprising:

mask logic circuits storing a mask identifying selected bytes within a packet of a particular format in the plurality of variant formats;

hash logic to generate a hash in response to the selected bytes; and

compare logic to compare the hash generated with an expected hash for the particular format.

34. The interface of claim 21, wherein at least a particular format in the plurality of variant formats supports packets having an optional field, the packet filter comprises:

mask logic circuits, having a mask for the particular format, and a mask modifier logic to modify the mask depending on detection, or not, of the optional field in the packet;

hash logic to generate a hash in response to the packet and the mask; and

compare logic to compare the hash generated with an expected hash for the particular format.

35. The interface of claim 34, wherein the optional field comprises a virtual local area network (VLAN) tag.

36. The interface of claim 34, wherein the optional field comprises a subnetwork attachment point (SNAP) header.

37. The interface of claim 21, including logic which signals the processor to process the data after at least part of the identified packet is stored in the buffer.

38. The interface of claim 21, including logic which signals the processor to process the data after the identified packet is stored in the buffer.

39. The interface of claim 21, including logic which, after at least part of the identified packet is stored in the buffer, stops the transferring of packets to the host, signals the processor to process the data, and re-starts the transferring of packets to the host in response to a result of said processing.

40. An integrated circuit for an interface to a network in which packets are received having a plurality of variant formats, and transferred to an active host system, the integrated circuit comprising:

an ethernet medium access control (MAC) unit on which incoming data is received at a data transfer rate of 100 Mbits per second or higher;

a First-In-First-Out (FIFO) buffer, coupled to the MAC unit, storing received packets;

a port, coupled with the FIFO buffer, through which transfer of packets to the host is executed;

a packet filter, coupled to the MAC unit, comprising a plurality of pattern match circuits, each pattern match circuit in the plurality including

mask logic circuits storing a mask identifying selected bytes within a packet of a particular format in the plurality of variant formats;

hash logic to generate a hash in response to the selected bytes;

compare logic to compare the hash generated with an expected hash for the particular format; and

logic to identify packets in response to the packet filter and generate an interrupt signal before the identified packets are transferred from the buffer to the host; and

a processor coupled with the buffer, and responsive to the interrupt signal from the packet filter that executes instructions to read and process data in the identified packets.

41. The integrated circuit of claim 40, wherein at least a particular format in the plurality of variant formats supports packets having an optional field, and at least one of the plurality of pattern match circuits includes mask modifier logic to modify the mask depending on detection, or not, of the optional field in the packet.

42. The integrated circuit of claim 41, wherein the optional field comprises a virtual local area network (VLAN) tag.

43. The integrated circuit of claim 41, wherein the optional field comprises a subnetwork attachment point (SNAP) header.

44. The integrated circuit of claim 40, wherein the processor comprises a routine to discover an internet protocol IP address of the host system.

45. The integrated circuit of claim 40, wherein the processor comprises a routine to issue a reboot command to the host system.

46. The integrated circuit of claim 40, wherein said logic to identify packets associates a control field with packets being stored in the buffer, and wherein the packet filter sets a variable in the control field to indicate whether the packet has one of the plurality of variant formats.