Phase lock loop having a robust bandwidth and a calibration method thereof

• US 6,570,947 B1
• Filed: 09/24/1999
• Issued: 05/27/2003
• Est. Priority Date: 09/24/1999
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Zipper, Eliav, Afek, Yachin, Zarubinsky, Michael
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US09/404,933
• Time in Patent Office: 1,341 Days
• Field of Search: 375/327, 375/376, 327/156, 327/159, 329/307, 331/2, 331/11, 331/16, 331/17, 331/177.R
• US Class Current: 375/376
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A phase lock loop having an bandwidth that does not depend upon N. The phase lock loop comprising: a controlled oscillator, a frequency divider by N, a phase detector for producing an error signal ER, and an adjustable converter, coupled to the phase detector and to the current controlled oscillator, for receiving ER and providing the controlled oscillator a control signal such that that the (Fico/N) ranges between a minimum value of Fmin and a maximal value of Fmax, wherein Fref=(Fmin+Fmax)/2.

Claims

1. A phase lock loop comprising:

a controlled oscillator, adapted to receive a control signal and to provide an output signal ICOS having a frequency Fico, Fico is responsive to the control signal;

a frequency divider, coupled to the controlled oscillator, for receiving ICOS and producing an output signal PD, having a frequency Fpd, wherein Fpd=Fico/N;

a phase detector, adapted to receive a reference clock signal REF, having frequency Fref, the phase detector is coupled to the frequency divider, for producing an error signal ER proportional to the phase difference between REF and PD; and

an adjustable converter, coupled to the phase detector and to the controlled oscillator, for receiving ER and providing to the controlled oscillator a control signal representative of a product of ER and a reference signal such that Fico is within a local range and Fref is statistically located in the middle of the local range.

2. The phase lock loop of claim 1 wherein the gain of the adjustable converter is proportional to 1/N.

3. The phase lock loop of claim 1 wherein the controlled oscillator is a current controlled oscillator and the adjustable converter comprises:

a main loop DAC, coupled to the phase detector and the current controlled oscillator, for converting the error signal ER to an analog control signal AS, ER ranging from a maximal value of ERmax to a minimal value of ERmin;

an adjustable current source, for providing a reference current Iref to the main loop DAC, to be multiplied by ER, wherein providing Iref and a nominal error signal ERnom=(ERmax+ERmin)/2 to main loop DAC causes the current controlled oscillator to output a signal having a frequency of Fico=Fref*N.

4. The phase lock loop of claim 3 wherein the adjustable current source comprises:

a current source, for providing a fixed current I1;

a current control unit, for providing a control word WR; and

a current reference DAC, coupled to the current source and to the current control unit, for receiving WR and for providing Iref, wherein Iref=I1*WR.

5. The phase lock loop of claim 4 wherein the main loop DAC is adapted to operate in higher frequencies than the current reference DAC.

6. The phase lock loop of claim 4 wherein the main loop DAC and the current reference DAC have a plurality of equally weighted current sources.

7. The phase locked loop of claim 3 wherein a capacitor is coupled to the output of the adjustable current source, for smoothing Iref.

8. A method for calibrating a phase lock loop, the phase lock loop having a phase detector for producing an error signal ER, a current controlled oscillator, a frequency divider, a main loop DAC, and an adaptable current source, the adaptable current source providing to the main loop DAC reference current Iref, the main loop DAC providing to the current controlled oscillator an analog signal AS representative of a product of the error signal ER and Iref, the method comprising of the steps of:

providing a predetermined value of the reference current to the main loop DAC, performing a frequency lock;

measuring the error signal ER provided by the phase detector to the main loop DAC, as a result of the frequency lock;

calculating a nominal value of the reference current to be provided to the main loop DAC, so that when a predetermined value of the control signal is provided to the main loop DAC, the current controlled oscillator will output a signal having a nominal frequency; and

providing the nominal value reference current to the main loop DAC.

9. The method of claim 8 wherein the adjustable current source comprises a current source, for providing a fixed current I1;

a current control unit, for providing a control word WR, for determining the size of Iref; and

a current reference DAC, coupled to the current source and the current control unit, for receiving WR and for providing Iref, wherein Iref=I*WR, wherein the step of providing the nominal value reference current involves providing a predetermined control word WRinit to the current reference DAC; and

wherein the step of calculating the nominal value of the reference current involves calculating a nominal control word WRnom to be provided to the current reference DAC.

10. The method of claim 8 wherein the calibration method is started when either of the following events occurs:

the phase lock loop is initialized;

the frequency divider used in calculating the nominal value of the reference current changes a division factor N; and

a frequency of a reference signal Fref is changed.

11. The method of claim 8 wherein the calibration method is started in any time period in which a stable operation of the phase lock loop is not required.