Random number generating apparatus

• US 6,571,263 B1
• Filed: 08/19/1999
• Issued: 05/27/2003
• Est. Priority Date: 08/19/1998
• Status: Expired due to Fees

• Current Assignee: Agency For Science Technology and Research, System Industrial Laboratory Do Limited
• Original Assignee: Japan Science And Technology Corpration, System Industrial Laboratory Do Limited
• Inventors: Nagai, Gouichiro
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/377,041
• Time in Patent Office: 1,377 Days
• Field of Search: 708/3, 708/250-251, 708/255, 708/801
• US Class Current: 708/3
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords

Abstract

A random number generating apparatus which is suitable for miniaturization and which can easily generate binary random numbers that are cryptographically secure is provided. The apparatus comprises: a semiconductor device having a junction; reverse bias applying circuit for applying a reverse bias voltage of a degree so as to cause a breakdown current in the junction; and a binarizing circuit for binarizing a noise signal created in a current path including said junction for generating random numbers from the binarized signal.

Claims

1. A random number signal generating apparatus comprising:

a semiconductor device having a junction;

a reverse bias applying circuit for applying a reverse bias voltage of a degree so as to cause a breakdown current in said junction;

an amplifying circuit for amplifying a noise signal created in a current path including said junction to produce an amplified noise signal;

DC-component removing means for removing a DC-component from the amplified noise signal to obtain a resultant noise signal;

sampling means for sampling the resultant noise signal in said DC-component removing means to output a sampling value sequence; and

a smoothing circuit for consecutively applying a logical calculation to each one of multiple sampling value blocks truncated from said sampling value sequence to generate a sequence of resultant values consisting of 0s and 1s as a random number signal, the logical calculations being performed such that occurrence probabilities of 0 and 1 in said resultant values are substantially equalized.

2. An apparatus according to claim 1, wherein said semiconductor device is a Zener diode.

3. A random number signal generating apparatus comprising:

a semiconductor device having a junction;

a reverse bias applying circuit for applying a reverse bias voltage of a degree so as to cause a breakdown current in said junction;

an amplifying circuit for amplifying a noise signal created in a current path including said junction to produce an amplified noise signal;

DC-component removing means for removing a DC-component from the amplified noise signal to obtain a resultant noise signal;

a comparison circuit for comparing the resultant noise signal in said DC-component removing means with a predetermined reference voltage for obtaining a binary signal;

sampling means for sampling said binary signal for obtaining a sampling value sequence consisting of 0s and 1s; and

a smoothing circuit for consecutively applying a logical calculation to each one of multiple sampling value blocks truncated from said sampling value sequence to generate a sequence of resultant values consisting of 0s and 1s as a random number signal, the logical calculations being performed such that occurrence probabilities of 0 and 1 in said resultant values are substantially equalized.

4. An apparatus according to claim 3, wherein said semiconductor device is a Zener diode.

5. An apparatus according to claim 4, further comprising:

a control circuit for controlling said reference voltage so as to substantially equalize an occurrence probability of 0 and 1 in said sampling value sequence.

6. An apparatus according to claim 3, further comprising:

a control circuit for controlling said reference voltage so as to substantially equalize an occurrence probability of 0 and 1 in said sampling value sequence.

7. An apparatus according to claim 3, wherein said predetermined reference voltage is a ground voltage.

8. A method for generating a random number signal, comprising the steps of:

utilizing a semiconductor device having a junction;

applying a reverse bias voltage to said junction and causing a breakdown current in said junction;

amplifying a noise signal created in a current path including said junction to produce an amplified noise signal;

removing a DC-component from the amplified noise signal to obtain a resultant noise signal,

sampling the resultant noise signal in said removing step to output a sampling value sequence as random numbers; and

consecutively applying a logical calculation to each one of multiple sampling value blocks truncated from said sampling value sequence to generate a sequence of resultant values consisting of 0s and 1s as a random number signal, the logical calculations being performed such that occurrence probabilities of 0 and 1 in said resultant values are substantially equalized.

9. A method according to claim 8, including:

utilizing a Zener diode as said semiconductor device.

10. A method for generating a random number signal, comprising the steps of:

utilizing a semiconductor device having a junction;

applying a reverse bias voltage to said junction and causing a breakdown current in said junction;

amplifying a noise signal created in a current path including said junction to produce an amplified noise signal;

removing a DC-component from the amplified noise signal to obtain a resultant noise signal;

comparing the resultant noise signal in said removing step with a predetermined reference voltage and obtaining a binary signal;

sampling said binary signal and obtaining a sampling value sequence consisting of 0s and 1s; and

consecutively applying a logical calculation to each one of multiple sampling value blocks truncated from said sampling value sequence to generate a sequence of resultant values consisting of 0s and 1s as a random number signal, the logical calculations being performed such that occurrence probabilities of 0 and 1 in said resultant values are substantially equalized.

11. A method according to claim 10, including:

utilizing a Zener diode as said semiconductor device.

12. A method according to claim 11, further comprising a step of controlling said reference voltage and substantially equalizing an occurrence probability of 0 and 1 in said sampling value sequence.

13. A method according to claim 10, further comprising a step of controlling said reference voltage and substantially equalizing an occurrence probability of 0 and 1 in said sampling value sequence.

14. A method according to claim 10, wherein said predetermined reference voltage is a ground voltage.