×

Method and apparatus for obtaining a scalar value directly from a vector register

  • US 6,571,328 B2
  • Filed: 08/01/2001
  • Issued: 05/27/2003
  • Est. Priority Date: 04/07/2000
  • Status: Expired due to Term
First Claim
Patent Images

1. An information processor, including a decoder for decoding instructions including at least some graphics instructions and at least one paired singles instruction, wherein the decoder is operable to decode a 32-bit paired-single-scalar-vector-multiply-add-high (ps_madds0x) instruction wherein a high order word of a paired singles register is used as a scalar, and further wherein the ps_madds0x instruction includes bits 0 through 31, wherein bits 0-5 encode a primary op code of 4, bits 6-10 designate a floating point destination register for storing the results of the instruction, bits 11-15 designate a first floating point register as a first source storing a first pair of 32-bit single-precision floating point values, bits 16-20 designate a second floating point register as a second source storing a second pair of 32-bit single-precision floating point values, bits 21-25 designate a third floating point register as a third source storing a third pair of 32-bit single-precision floating point values, bits 26-30 encode a secondary op code of 14 and bit 31 comprises a record bit indicating updating of a condition register, and further wherein the secondary op code indicates that the high order word is to be used as the scalar.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×