Semiconductor device manufacturing method

• US 6,573,112 B2
• Filed: 09/11/2002
• Issued: 06/03/2003
• Est. Priority Date: 09/18/1998
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Tanaka, Shinji, Ohta, Hiroyuki, Kono, Ryuji, Miura, Hideo, Endo, Yoshishige, Kanamaru, Masatoshi, Ariga, Akihiko, Ban, Naoto, Aoki, Hideyuki, Hosogane, Atsushi
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Luk, Olivia T
• Application Number:
  US10/238,690
• Publication Number:
  US 20030027365A1
• Time in Patent Office: 265 Days
• Field of Search: 438/14, 438/15, 438/16, 437/8, 371/22.1
• US Class Current: 438/14
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys

Abstract

Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.

Claims

1. A jig to be used in a semiconductor device inspection method of inspecting semiconductor device chips obtained by forming a plurality of large-scale integrated circuits over the semiconductor wafer and cutting the semiconductor wafer into individual LSI chips, in which the method comprises the steps of:

rearranging said cut LSI chips and integrating a predetermined number N of LSI chips;

inspecting said number N of cut LSI chips; and

screening to select LSI chips basis on an inspection result obtained in said inspecting step;

wherein said rearranging and integrating step is performed by using a jig for integration; and

wherein said jig is formed of a material whose coefficient of thermal expansion is approximately equal to the LSI chips, and an accommodating portion for rearranging the predetermined number N of cut LSI chips is formed in part of said jig.

2. A jig to be used in a semiconductor device inspection method according to claim 1, wherein including a plate-shaped base formed of a material whose coefficient of thermal expansion is approximately equal to the LSI chips, and a tray which is disposed above said base and is formed of a material whose coefficient of thermal expansion is approximately equal to the LSI chips, openings for rearranging the predetermined number N of cut LSI chips being formed in said tray by the predetermined number N.

3. A jig to be used in a semiconductor device inspection method according to claim 2, wherein at least either one of said base and said tray is formed of silicon.

4. A jig to be used in a semiconductor device inspection method according to claim 2, wherein at least either one of said base and said tray is formed of aluminum nitride.

5. A jig to be used in a semiconductor device inspection method according to claim 2, wherein including a plate-shaped contactor to be disposed above said tray, one surface of said contactor being provided with probe portions to be respectively electrically connected to electrode portions of the predetermined number N of LSI chips rearranged in said jig, while the other surface of said contactor is provided with secondary electrodes to be respectively electrically connected to said probe portions.

6. A jig to be used in a semiconductor device inspection method according to claim 5, wherein said contactor is formed of silicon.

7. A jig to be used in a semiconductor device inspection method according to claim 5, wherein said contactor is formed of aluminum nitride.

8. A jig to be used in a semiconductor device inspection method according to claim 5, wherein said number N of secondary electrodes which are disposed over the other surface of said contactor are formed at a pitch of 0.5 mm to 1.5 mm.

9. A jig to be used in a step of inspection for a large-scale integrated circuit (LSI) chip having a main surface and a rear surface opposite from the main surface, the main surface having circuits formed thereon, the jig comprising:

openings with a size commensurate with the dimensions of the LSI chip so as to integrate the LSI chip in the jig such that the rear surface of each chip is in contact with the jig and the main surface is exposed for inspection;

an inspecting portion which contacts the main surface during inspection; and

wherein at least on part of the jig having the openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chip.

10. A jig to be used in a step of inspection for a semiconductor device having a main surface and a rear surface opposite from the main surface, the main surface having circuits formed thereon, the jig comprising:

openings with a size commensurate with the dimensions of the semiconductor device so as to integrate the semiconductor device in the jig such that the rear surface of each device is in contact with the jig and the main surface is exposed for inspection;

an inspecting portion which electrically contacts the circuits during inspection; and

wherein at least on part of the jig having the openings has a coefficient of thermal expansion that is approximately equal to that of the semiconductor device.