Method to fabricate self-aligned source and drain in split gate flash
First Claim
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1. A method of fabricating a new structure for source/drain bit lines in arrays of MOSFET devices comprising:
- providing a partially processed array of MOSFET devices having active areas arranged in columns which are surrounded by insulator filled isolation regions and having formed, but not patterned, all layers comprising gate structures that are adjacent to source/drain regions, etching, in rows, all layers comprising gate structures that are adjacent to source/drain regions and insulator filled isolation regions to form openings that are aligned in rows passing source/drain positions;
performing ion implantation into the silicon under said openings creating continuous conductive regions forming rows through the silicon substrate under said openings; and
filling said openings with insulating material.
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Abstract
A new structure is disclosed for source/drain bit lines in arrays of MOSFET devices. Rows of conducting regions are formed by ion implantation through openings adjacent to gate structures and in isolation regions separating columns of active areas of the arrays. The openings are filled with insulating material.
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Citations
24 Claims
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1. A method of fabricating a new structure for source/drain bit lines in arrays of MOSFET devices comprising:
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providing a partially processed array of MOSFET devices having active areas arranged in columns which are surrounded by insulator filled isolation regions and having formed, but not patterned, all layers comprising gate structures that are adjacent to source/drain regions, etching, in rows, all layers comprising gate structures that are adjacent to source/drain regions and insulator filled isolation regions to form openings that are aligned in rows passing source/drain positions;
performing ion implantation into the silicon under said openings creating continuous conductive regions forming rows through the silicon substrate under said openings; and
filling said openings with insulating material. - View Dependent Claims (2, 3, 4, 5)
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6. A method to fabricate self-aligned source/drain lines in split gate flash memory arrays, comprising:
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providing an extensive p-type semiconductor region on a semiconductor substrate;
defining columns of active regions by surrounding said active regions with oxide filled isolation regions;
performing a first threshold voltage adjust implant;
forming a floating gate oxide layer over the surface of said active regions;
forming a poly 1 layer;
forming a photoresist layer and patterning said photoresist layer to etch said poly 1 layer so that after etching said poly 1 layer is disposed over said active regions;
performing a poly 1 layer etch;
removing the photoresist layer;
forming sequentially, a first insulating layer, a poly 2 layer, a second insulating layer, a poly 3 layer and a first oxide layer;
forming another photoresist layer and patterning the photoresist to form, upon etching, two kinds of interposed openings in a direction perpendicular to the active region;
openings for source/drain lines that could be narrower than openings for erase gates;
etching sequentially, said first oxide layer, said poly 3 layer, said second insulating layer, said poly 2 layer and said first insulating layer;
removing said other photoresist layer;
forming a third photoresist layer and patterning the photoresist so as to deepen, upon etching, only the openings for source/drain lines;
etching said poly 1 layer;
etching floating gate oxide and oxide of said isolation regions;
performing a source/drain ion implantation;
removing the third photoresist layer;
forming a second oxide layer and etching said second oxide layer so that the source/drain openings are filled with said second oxide and so that sidewall spacers, composed of said second oxide, remain;
etching exposed poly 1 layer and poly 3 layer;
performing a second threshold adjust implant for the erase gates;
etching exposed floating gate oxide;
forming an erasing gate oxide layer;
forming a poly 4 layer;
forming a fourth photoresist layer and patterning the photoresist for erase gate lines disposed over the active regions;
etching said poly 4 layer;
removing the fourth photoresist layer. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification