Process for producing an MOS field effect transistor with a recombination zone

• US 6,573,145 B2
• Filed: 11/13/2001
• Issued: 06/03/2003
• Est. Priority Date: 11/10/2000
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kröner, Friedrich
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): BROPHY, JAMIE LYNN
• Application Number:
  US10/008,797
• Publication Number:
  US 20020081785A1
• Time in Patent Office: 567 Days
• Field of Search: 438/157, 438/283, 438/284, 438/589
• US Class Current: 438/284
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A process having a robust process sequence for producing an MOS field effect transistor having a horizontal buried gate formed of polysilicon and a recombination zone provided at the surface of the transistor includes the steps of producing the horizontal polysilicon gate first and then introducing the recombination zone. The process allows producing a transistor without encountering problems caused by the insufficient high-temperature compatibility of metals.

Claims

1. A process for producing an MOS field effect transistor, the process which comprises:

providing a base material including a buried oxide layer and an active silicon layer;

structuring the base material having the buried oxide layer and the active silicon layer for providing a structured region in the base material;

depositing silicon onto the structured region of the base material and outside the structured region of the base material by using an epitaxial deposition process;

contra-doping a channel region;

exposing partial regions of the buried oxide layer;

performing an etching process for removing any silicon oxide at least from the structured region of the base material;

forming a gate oxide and a horizontal buried gate formed of polysilicon;

structuring the polysilicon;

producing a source doping in a structured manner;

producing a dielectric in a structured manner;

providing a recombination zone at a surface region of the MOS field effect transistor by structuring a metal to be used for recombination; and

producing gate and source contacts for the MOS field effect transistor.

2. The process according to claim 1, which comprises using a wafer-bonded SOI material as the base material.

3. The process according to claim 1, which comprises producing the buried oxide layer by implanting oxygen.

4. The process according to claim 1, which comprises producing the buried oxide layer by implanting oxygen in a structured manner.

5. The process according to claim 1, which comprises providing the active silicon layer such that the active silicon layer is thinner than the buried oxide layer.

6. A process for producing an MOS field effect transistor, the process which comprises:

providing a base material;

implanting oxygen into the base material in a structured manner for providing a buried oxide layer;

contra-doping a channel region;

exposing partial regions of the buried oxide layer;

performing an etching process for removing any silicon oxide;

forming a gate oxide and a horizontal buried gate formed of polysilicon;

structuring the polysilicon;

producing a source doping in a structured manner;

producing a dielectric in a structured manner;

providing a recombination zone at a surface region of the MOS field effect transistor by structuring a metal to be used for recombination; and

producing gate and source contacts for the MOS field effect transistor.