Methods for improving carrier mobility of PMOS and NMOS devices

• US 6,573,172 B1
• Filed: 09/16/2002
• Issued: 06/03/2003
• Est. Priority Date: 09/16/2002
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ngo, Minh Van, Hui, Angela, En, William George
• Primary Examiner(s): Ho, Hoai
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US10/244,439
• Time in Patent Office: 260 Days
• Field of Search: 438/153, 438/154, 438/157, 438/170, 438/197, 438/204, 438/236, 438/253, 438/626
• US Class Current: 438/626
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

Methods are described for fabricating semiconductor devices, in which a tensile film is formed over PMOS transistors to cause a compressive stress therein and a compressive film is formed over NMOS transistors to achieve a tensile stress therein, by which improved carrier mobility is facilitated in both PMOS and NMOS devices.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a PMOS transistor and an NMOS transistor in a wafer;

forming a tensile film over the PMOS transistor; and

forming a compressive film over the NMOS transistor.

2. The method of claim 1, wherein forming the tensile film comprises forming a first nitride layer over the PMOS transistor and wherein forming the compressive film comprises forming a second nitride layer over the NMOS transistor.

3. The method of claim 2, wherein forming the first nitride layer comprises causing a compressive stress in at least a portion of the PMOS transistor and wherein forming the second nitride layer comprises causing a tensile stress in at least a portion of the NMOS transistor.

4. The method of claim 3, wherein forming the first nitride layer comprises depositing a first nitride material over the PMOS transistor using a first PECVD process with a high frequency RF plasma excitation power of about 400 W or more, and wherein forming the second nitride layer comprises depositing a second nitride material over the NMOS transistor using a second PECVD process with a high frequency RF plasma excitation power of about 400 W or less.

5. The method of claim 4, wherein the first PECVD process comprises providing high frequency RF plasma excitation power at about 400 W or more and about 600 W or less at a pressure of about 1.7 Torr or more and about 2.1 Torr or less using NH₃, SiH₄, and N₂ gases, and wherein the second PECVD process comprises providing high frequency RF plasma excitation power at about 300 W or more and about 400 W or less and providing low frequency RF heater power at about 400 W or more and about 500 W or less at a pressure of about 1.7 Torr or more and about 2.1 Torr or less using NH₃, SiH₄, and N₂ gases.

6. The method of claim 5, wherein the first PECVD process comprises providing NH₃ gas at a flow rate of about 2 slm or more and about 4 slm or less, providing SiH₄ gas at a flow rate of about 300 sccm or more and about 400 sccm or less, and providing N₂ gas at a flow rate of about 2 slm or more and about 4 slm or less, and wherein the second PECVD process comprises providing NH₃ gas at a flow rate of about 2 slm or more and about 4 slm or less, providing SiH₄ gas at a flow rate of about 300 sccm or more and about 400 sccm or less, and providing N₂ gas at a flow rate of about 2 slm or more and about 4 slm or less.

7. The method of claim 5, wherein forming the first nitride layer comprises causing a compressive stress in a channel region of the PMOS transistor and wherein forming the second nitride layer comprises causing a tensile stress in a channel region of the NMOS transistor.

8. The method of claim 7, wherein forming the first nitride layer over the PMOS transistor comprises depositing the first nitride material over the wafer using the first PECVD process and selectively removing first nitride material from over the NMOS transistor using a first patterned etch process, and wherein forming the second nitride layer over the NMOS transistor comprises depositing the second nitride material over the wafer after the first patterned etch process using the second PECVD process and selectively removing second nitride material from over the PMOS transistor using a second patterned etch process.

9. The method of claim 8, comprising forming an oxide layer over the wafer following the first patterned etch process and prior to the second PECVD process.

10. The method of claim 4, wherein forming the first nitride layer comprises depositing the first nitride material over the PMOS transistor using the first PECVD process with a high frequency RF plasma excitation power of about 400 W or more and about 600 W or less, and wherein forming the second nitride layer comprises depositing the second nitride material over the NMOS transistor using the second PECVD process with a high frequency RF plasma excitation power of about 300 W or more and about 400 W or less.

11. The method of claim 10, wherein forming the first nitride layer comprises causing a compressive stress in a channel region of the PMOS transistor and wherein forming the second nitride layer comprises causing a tensile stress in a channel region of the NMOS transistor.

12. The method of claim 11, wherein forming the first nitride layer over the PMOS transistor comprises depositing the first nitride material over the wafer using the first PECVD process and selectively removing first nitride material from over the NMOS transistor using a first patterned etch process, and wherein forming the second nitride layer over the NMOS transistor comprises depositing the second nitride material over the wafer after the first patterned etch process using the second PECVD process and selectively removing second nitride material from over the PMOS transistor using a second patterned etch process.

13. The method of claim 3, wherein forming the first nitride layer comprises causing a compressive stress in a channel region of the PMOS transistor and wherein forming the second nitride layer comprises causing a tensile stress in a channel region of the NMOS transistor.

14. The method of claim 3, wherein forming the first nitride layer over the PMOS transistor comprises depositing the first nitride material over the wafer using the first PECVD process and selectively removing first nitride material from over the NMOS transistor using a first patterned etch process, and wherein forming the second nitride layer over the NMOS transistor comprises depositing the second nitride material over the wafer after the first patterned etch process using the second PECVD process and selectively removing second nitride material from over the PMOS transistor using a second patterned etch process.

15. The method of claim 14, comprising forming an oxide layer over the wafer following the first patterned etch process and prior to the second PECVD process.

16. The method of claim 2, wherein forming the tensile film comprises causing a compressive stress in a channel region of the PMOS transistor and wherein forming the compressive film comprises causing a tensile stress in a channel region of the NMOS transistor.

17. The method of claim 16, wherein forming the tensile film over the PMOS transistor comprises depositing a first nitride material over the wafer using a first PECVD process and selectively removing first nitride material from over the NMOS transistor using a first patterned etch process, and wherein forming the compressive film over the NMOS transistor comprises depositing a second nitride material over the wafer after the first patterned etch process using a second PECVD process and selectively removing second nitride material from over the PMOS transistor using a second patterned etch process.

18. The method of claim 17, comprising forming an oxide layer over the wafer following the first patterned etch process and prior to the second PECVD process.

19. The method of claim 1, wherein forming the tensile film comprises causing a compressive stress in a channel region of the PMOS transistor and wherein forming the compressive film comprises causing a tensile stress in a channel region of the NMOS transistor.

20. A method of improving carrier mobility of PMOS and NMOS transistors in the fabrication of CMOS devices in a wafer, comprising:

selectively forming a tensile film over the PMOS transistor and not over the NMOS transistor in the wafer to create a compressive stress in a channel region of the PMOS transistor; and

selectively forming a compressive film over the NMOS transistor and not over the PMOS transistor to create a tensile stress in a channel region of the NMOS transistor.

21. The method of claim 20, wherein forming the tensile film comprises forming a first nitride layer over the PMOS transistor and not over the NMOS transistor, and wherein forming the compressive film comprises forming a second nitride layer over the NMOS transistor and not over the PMOS transistor.

22. The method of claim 21, wherein selectively forming the tensile film over the PMOS transistor and not over the NMOS transistor comprises depositing a first nitride material over the wafer using a first PECVD process and selectively removing first nitride material from over the NMOS transistor using a first patterned etch process, and wherein selectively forming the compressive film over the NMOS transistor and not over the PMOS transistor comprises depositing a second nitride material over the wafer after the first patterned etch process using a second PECVD process and selectively removing second nitride material from over the PMOS transistor using a second patterned etch process.

23. The method of claim 22, comprising forming an oxide layer over the wafer following the first patterned etch process and prior to the second PECVD process.

24. The method of claim 23, wherein the first PECVD process comprises providing high frequency RF plasma excitation power at about 400 W or more and about 600 W or less, and wherein the second PECVD process comprises providing high frequency RF plasma excitation power at about 300 W or more and about 400 W or less and providing low frequency RF heater power at about 400 W or more and about 500 W or less.

25. The method of claim 24, wherein the first PECVD process comprises providing NH₃ gas at a flow rate of about 2 slm or more and about 4 slm or less, providing SiH₄ gas at a flow rate of about 300 sccm or more and about 400 sccm or less, and providing N₂ gas at a flow rate of about 2 slm or more and about 4 slm or less at a pressure of about 1.7 Torr or more and about 2.1 Torr or less, and wherein the second PECVD process comprises providing NH₃ gas at a flow rate of about 2 slm or more and about 4 slm or less, providing SiH₄ gas at a flow rate of about 300 sccm or more and about 400 sccm or less, and providing N₂ gas at a flow rate of about 2 slm or more and about 4 slm or less at a pressure of about 1.7 Torr or more and about 2.1 Torr or less.

26. A method of fabricating CMOS devices in a wafer, comprising:

forming a PMOS transistor and an NMOS transistor in the wafer;

forming a tensile film over the wafer;

selectively removing the tensile film from over the NMOS transistor while leaving the tensile film over the PMOS transistor to provide a compressive stress in at least a portion of the PMOS transistor;

forming a compressive film over the wafer; and

selectively removing the compressive film from over the PMOS transistor while leaving the compressive film over the NMOS transistor to provide a tensile stress in at least a portion of the NMOS transistor.

27. The method of claim 26, wherein forming the tensile film comprises depositing a first nitride material over the wafer using a first PECVD process, and wherein forming the compressive film comprises depositing a second nitride material over the wafer after removing the tensile film from over the NMOS transistor using a second PECVD process.

28. The method of claim 27, wherein the first PECVD process comprises providing high frequency RF plasma excitation power at about 400 W or more and about 600 W or less, and wherein the second PECVD process comprises providing high frequency RF plasma excitation power at about 300 W or more and about 400 W or less and providing low frequency RF heater power at about 400 W or more and about 500 W or less.

29. The method of claim 28, wherein the first PECVD process comprises providing NH₃ gas at a flow rate of about 2 slm or more and about 4 slm or less, providing SiH₄ gas at a flow rate of about 300 sccm or more and about 400 sccm or less, and providing N₂ gas at a flow rate of about 2 slm or more and about 4 slm or less at a pressure of about 1.7 Torr or more and about 2.1 Torr or less, and wherein the second PECVD process comprises providing NH₃ gas at a flow rate of about 2 slm or more and about 4 slm or less, providing SiH₄ gas at a flow rate of about 300 sccm or more and about 400 sccm or less, and providing N₂ gas at a flow rate of about 2 slm or more and about 4 slm or less at a pressure of about 1.7 Torr or more and about 2.1 Torr or less.

30. The method of claim 26, wherein selectively removing the tensile film comprises performing a first patterned etch process after the first PECVD deposition process to remove the tensile film from over the NMOS transistor while leaving the tensile film over the PMOS transistor, and wherein selectively removing the compressive film comprises performing a second patterned etch process after the second PECVD deposition process to remove the compressive film from over the PMOS transistor while leaving the compressive film over the NMOS transistor.