Parasitic surface transfer transistor cell (PASTT cell) for bi-level and multi-level NAND flash memory

• US 6,573,556 B2
• Filed: 07/01/2002
• Issued: 06/03/2003
• Est. Priority Date: 05/17/2001
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Doong, Kelvin Yin-Yuh, Hsu, Ching-Hsiang
• Primary Examiner(s): Dang, Phuc T.
• Application Number:
  US10/186,529
• Publication Number:
  US 20020173107A1
• Time in Patent Office: 337 Days
• Field of Search: 257/314, 257/315, 257/320, 257/346, 257/366, 257/386, 257/403
• US Class Current: 257/315
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A new Flash memory cell device with a parasitic surface transfer transistor (PASTT) and a method of manufacture are achieved. The device comprises, first, a semiconductor substrate. The semiconductor substrate further comprises an active area and an isolation barrier region. A source junction is in the active area. A drain junction is in the active area. A cell channel is in the active area extending from the drain junction to the source junction. A parasitic channel is in the active area on the top surface of the semiconductor substrate extending from the drain junction to the source junction. The parasitic channel is bounded on one side by the isolation barrier region and on another side by the cell channel. A floating gate comprises a first conductive layer overlying the cell channel with a tunneling oxide layer therebetween. The floating gate does not overlie the parasitic channel. A control gate comprises a second conductive layer overlying the floating gate with an interlevel dielectric layer therebetween. A parasitic surface transfer-transistor (PASTT) gate comprises the second conductive layer overlying the parasitic channel with the interlevel dielectric layer therebetween.

Claims

1. An Flash memory cell device with a parasitic surface transfer transistor (PASTT) comprising:

a semiconductor substrate comprising an active area and an isolation barrier region;

a source junction in said active area;

a drain junction in said active area;

a cell channel in said active area extending from said drain junction to said source junction;

a parasitic channel in said active area on the top surface of said semiconductor substrate extending from said drain junction to said source junction, bounded on one side by said isolation barrier region, and bounded on another other side by said cell channel;

a floating gate comprising a first conductive layer overlying said cell channel with a tunneling oxide layer therebetween wherein said floating gate does not overlie said parasitic channel;

a control gate comprising a second conductive layer overlying said floating gate with an interlevel dielectric layer therebetween; and

a parasitic surface transfer transistor (PASTT) gate comprising said second conductive layer overlying said parasitic channel with said interlevel dielectric layer therebetween wherein said PASTT gate inverts said parasitic channel to turn ON said PASTT at a parasitic threshold voltage.

2. The device according to claim 1 wherein said isolation barrier region comprises shallow trench isolation.

3. The device according to claim 1 wherein said parasitic threshold voltage is between about 0.5 Volts and 4.5 Volts.

4. The device according to claim 1 wherein said parasitic channel is ion implanted to control said parasitic threshold voltage.

5. The device according to claim 1 wherein said parasitic channel comprises two sections, one on each side of said cell channel.

6. The device according to claim 1 wherein said parasitic channel has a width of between about 0.025 microns and 0.070 microns between said cell channel and said isolation harrier region.

7. The device according to claim 1 further comprising:

a lightly doped region in said drain junction;

a lightly doped region in said source junction; and

sidewall spacers adjacent to said floating gate and to said control gate.

8. The device according to claim 1 wherein said interlevel dielectric layer comprises a laminated stack (ONO) of silicon dioxide, silicon nitride, and silicon dioxide.

9. The device according to claim 1 wherein said first conductive layer comprises polysilicon.

10. The device according to claim 1 wherein said second conductive layer comprises polysilicon.

11. An Flash memory cell device with a parasitic surface transfer transistor (PASTT) comprising:

a semiconductor substrate comprising an active area and a shallow trench isolation;

a source junction in said active area;

a drain junction in said active area;

a cell channel in said active area extending from said drain junction to said source junction;

parasitic channels in said active area on the top surface of said semiconductor substrate extending from said drain junction to said source junction, bounded on one side by said isolation barrier region, and bounded on another other side by said cell channel;

a floating gate comprising a first polysilicon layer overlying said cell channel with a tunneling oxide layer therebetween wherein said floating gate does not overlie said parasitic channels;

a control gate comprising a second polysilicon layer overlying said floating gate with an interlevel dielectric layer therebetween; and

a parasitic surface transfer transistor (PASTT) gate comprising said second polysilicon layer overlying said parasitic channels with said interlevel dielectric layer therebetween wherein said PASTT gate inverts said parasitic channels to turn ON said PASTT at a parasitic threshold voltage.

12. The device according to claim 11 wherein said parasitic threshold voltage is between about 0.5 Volts and 4.5 Volts.

13. The device according to claim 11 wherein said parasitic channels are ion implanted to control said parasitic threshold voltage.

14. The device according to claim 11 wherein said parasitic channels have a width of between about 0.025 microns and 0.070 microns between said cell channel and said isolation barrier region.

15. The device according to claim 11 further comprising:

a lightly doped region in said drain junction;

a lightly doped region in said source junction; and

sidewall spacers adjacent to said floating gate and to said control gate.

16. The device according to claim 11 wherein said interlevel dielectric layer comprises a laminated stack (ONO) of silicon dioxide, silicon nitride, and silicon dioxide.