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Parasitic surface transfer transistor cell (PASTT cell) for bi-level and multi-level NAND flash memory

  • US 6,573,556 B2
  • Filed: 07/01/2002
  • Issued: 06/03/2003
  • Est. Priority Date: 05/17/2001
  • Status: Expired due to Term
First Claim
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1. An Flash memory cell device with a parasitic surface transfer transistor (PASTT) comprising:

  • a semiconductor substrate comprising an active area and an isolation barrier region;

    a source junction in said active area;

    a drain junction in said active area;

    a cell channel in said active area extending from said drain junction to said source junction;

    a parasitic channel in said active area on the top surface of said semiconductor substrate extending from said drain junction to said source junction, bounded on one side by said isolation barrier region, and bounded on another other side by said cell channel;

    a floating gate comprising a first conductive layer overlying said cell channel with a tunneling oxide layer therebetween wherein said floating gate does not overlie said parasitic channel;

    a control gate comprising a second conductive layer overlying said floating gate with an interlevel dielectric layer therebetween; and

    a parasitic surface transfer transistor (PASTT) gate comprising said second conductive layer overlying said parasitic channel with said interlevel dielectric layer therebetween wherein said PASTT gate inverts said parasitic channel to turn ON said PASTT at a parasitic threshold voltage.

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