Vertical MOSFET with asymmetrically graded channel doping

• US 6,573,561 B1
• Filed: 03/11/2002
• Issued: 06/03/2003
• Est. Priority Date: 03/11/2002
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG), International Business Machines Corporation
• Original Assignee: Infineon Technologies AG, International Business Machines Corporation
• Inventors: Divakaruni, Ramachandra, Chidambarrao, Dureseti, Mandelman, Jack A., McStay, Kevin
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US10/096,192
• Time in Patent Office: 449 Days
• Field of Search: 257/328, 257/329, 257/335, 257/336
• US Class Current: 257/335
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.

Claims

1. A vertical transistor formed in a DRAM array in a semiconductor substrate comprising:

a trench extending vertically into said substrate and containing a transistor disposed above a capacitor;

an upper transistor electrode formed in a top level of said transistor;

a lower transistor electrode formed in a lower level of said transistor, the vertical distance between said upper transistor electrode and said lower transistor electrode being less than 200 nm;

a gate dielectric extending downwardly from said upper transistor electrode toward said lower transistor electrode and abutting a transistor body formed in said semiconductor substrate, said transistor body being disposed immediately adjacent to said lower electrode;

a threshold dopant distribution of dopant disposed in said transistor body, said dopant distribution having a maximum value of dopant concentration at a peak level closer to said upper transistor electrode than to said lower transistor electrode;

a transistor gate disposed in said trench adjacent said gate dielectric on a side opposite said transistor body; and

an insulating plug disposed in said trench that separates said transistor gate and an inner electrode of said capacitor and that further defines the position of said lower transistor electrode, whereby the vertical position of said lower transistor electrode fluctuates in accordance with fluctuations in the vertical position of said insulating plug and in which said threshold dopant distribution has a concentration value that declines as a function of depth below said peak level, so that said concentration value of said threshold dopant distribution in said channel has a minimum value near said lower transistor electrode, and so that the threshold of said transistor is insensitive to said fluctuations in the position of said insulating plug.

2. A transistor according to claim 1, in which said threshold dopant distribution has a concentration value that declines as a function of depth below said peak level, whereby said concentration value of said threshold dopant distribution in said channel has a minimum value near said lower transistor electrode and thereby reduces leakage of stored charge.

3. A transistor according to claim 1, in which said maximum value of said dopant concentration is located at a distance below said upper transistor electrode that is no more than one third the total distance between said upper transistor electrode and said lower transistor electrode.

4. A transistor according to claim 2, in which said maximum value of said dopant concentration is located at a distance below said upper transistor electrode that is no more than one third the total distance between said upper transistor electrode and said lower transistor electrode.

5. A DRAM integrated circuit comprising an array of memory cells comprising a vertical transistor disposed above and connected to a capacitor, said vertical transistor extending downwardly from an upper transistor electrode toward a capacitor electrode and comprising:

a lower transistor electrode formed in a lower level of said transistor, the vertical distance between said upper transistor electrode and said lower transistor electrode being less than 200 nm;

a gate dielectric extending downwardly from said upper transistor electrode toward said lower transistor electrode and abutting a transistor body formed in said semiconductor substrate, said transistor body being disposed immediately adjacent to said lower electrode;

a threshold dopant distribution of dopant disposed in said transistor body, said dopant distribution having a maximum value of dopant concentration at a peak level closer to said upper transistor electrode than to said lower transistor electrode;

a transistor gate disposed in said trench adjacent said gate dielectric on a side opposite said transistor body; and

an insulating plug disposed in said trench that separates said transistor gate and an inner electrode of said capacitor and that further defines the position of said lower transistor electrode, whereby the vertical position of said lower transistor electrode fluctuates in accordance with fluctuations in the vertical position of said insulating plug and in which said threshold dopant distribution has a concentration value that declines as a function of depth below said peak level, so that said concentration value of said threshold dopant distribution in said channel has a minimum value near said lower transistor electrode, and so that the threshold of said transistor is insensitive to said fluctuations in the position of said insulating plug.

6. A DRAM according to claim 5, in which said threshold dopant distribution has a concentration value that declines as a function of depth below said peak level, whereby said concentration value of said threshold dopant distribution in said channel has a minimum value near said lower transistor electrode and thereby reduces leakage of stored charge.

7. A DRAM according to claim 5, in which said maximum value of said dopant concentration is located at a distance below said upper transistor electrode that is no more than one third the total distance between said upper transistor electrode and said lower transistor electrode.

8. A DRAM according to claim 6, in which said maximum value of said dopant concentration is located at a distance below said upper transistor electrode that is no more than one third the total distance between said upper transistor electrode and said lower transistor electrode.