SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs

• US 6,573,563 B2
• Filed: 06/01/2001
• Issued: 06/03/2003
• Est. Priority Date: 02/07/2001
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Tae-Jung, Lee, Soo-Cheol
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US09/872,429
• Publication Number:
  US 20020105032A1
• Time in Patent Office: 732 Days
• Field of Search: 257/347, 257/349, 257/373, 257/374, 257/382, 257/396, 257/510, 257/515, 257/517, 365/189.09, 438/155
• US Class Current: 257/349
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A silicon-on-insulator (SOI) integrated, circuit is provided. A plurality of transistor active regions and at least one body contact active region are formed on an SOI substrate. A semiconductor residue layer, which is thinner than the transistor active regions and the body contact active region, is disposed between the transistor active regions and the body contact active region. The transistor active regions, the body contact active region and the semiconductor residue layer are disposed on a buried insulating layer of the SOI substrate. The semiconductor residue layer is covered with a partial trench isolation layer. A bar-shaped full trench isolation layer is interposed between the adjacent transistor active regions. The full trench isolation layer is in contact with sidewalls of the transistor active regions adjacent thereto and is in contact with the buried insulating layer between the adjacent transistor active regions. An insulated gate pattern crosses over the respective transistor active regions. The insulated gate pattern is disposed to be parallel with the full trench isolation layer.

Claims

1. A silicon-on-insulator (SOI) semiconductor integrated circuit formed on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer, the integrated circuit comprising:

a plurality of transistor active regions in a predetermined region of the semiconductor layer, the plurality of transistor active regions being of the same transistor conductivity type;

at least one body contact active region spaced apart from the transistor active regions, the body contact active region including a portion of the semiconductor layer;

a semiconductor residue layer disposed over the entire surface of the buried insulating layer between the transistor active regions and the body contact active region, the semiconductor residue layer being thinner than the semiconductor layer;

a partial trench isolation layer disposed on the semiconductor residue layer;

an insulated gate pattern crossing over the respective transistor active regions; and

a bar-shaped full trench isolation layer interposed between the adjacent transistor active regions and running parallel with the gate pattern, the full trench isolation layer being in contact with the buried insulating layer between the adjacent active regions and being in contact with the entire sidewalls of the transistor active regions that are parallel with the gate pattern.

2. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, wherein the first conductivity type is one of P-type and N-type.

3. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, wherein the semiconductor layer is a silicon layer.

4. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, further comprising source/drain regions formed at the transistor active regions, the source/drain regions being located at both sides of the insulated gate pattern, the source/drain regions having a second conductivity type opposite to the first conductivity type and being in contact with the buried insulating layer.

5. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, further comprising a well contact region formed at the body contact active region, the well contact region having the first conductivity type.