Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect

• US 6,573,606 B2
• Filed: 06/14/2001
• Issued: 06/03/2003
• Est. Priority Date: 06/14/2001
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Sambucetti, Carlos Juan, Lustig, Naftali Eliahu, Agarwala, Birenda Nath, Hu, Chao-Kun, Chen, Xiaomeng, Seo, Soon-Cheon, Greco, Stephen Edward
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US09/881,444
• Publication Number:
  US 20030001275A1
• Time in Patent Office: 719 Days
• Field of Search: 257/754, 257/762, 257/765, 257/767, 257/770, 257/771, 438/683, 438/686, 438/685, 438/687, 438/693, 438/745, 438/756, 438/757, 438/638, 438/653, 438/624, 438/639, 438/633
• US Class Current: 257/762
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A—X—Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

Claims

1. A metallization interface in integrated circuit fabrication for use in joining a copper interconnect member to other electrical network members,

comprising in combination

a copper interconnect member positioned in a dielectric substrate,

said copper interconnect member being surrounded by an electrically isolating liner in said substrate,

said copper interconnect member surrounded by said electrically isolating liner combination being further surrounded at a surface of said dielectric substrate by a layer of a hard mask material, and,

a single alloy capping layer of CoWP in the proportions 86-90% wt. of Co, 1-5% wt of W and 6-12% wt of P, 50-300 Angstroms thick in contact with the surface of said copper interconnect member at said hardmask surface.

2. A metallization interface in integrated circuit fabrication for use in joining a copper interconnect member to other electrical network members,

comprising in combination

a copper interconnect member positioned in a dielectric substrate,

said copper interconnect member being surrounded by an electrically isolating liner in said substrate,

said copper interconnect member surrounded by said electrically isolating liner combination being further surrounded at a surface of said dielectric substrate by a layer of a hard mask material, and,

a single alloy capping layer of NiWP in the proportions 86-90% wt. of Ni, 1-5% wt of W and 6-12% wt of P, 50-300 Angstroms thick in contact with the surface of said copper interconnect member at said hardmask surface.

3. The process of providing a copper interconnect metallization interface in integrated circuit fabrication for use in joining a copper interconnect member to other electrical network members,

comprising the steps of:

positioning in a substrate, extending to and exposed at a surface thereof, a copper interconnect member, surrounded by an electrically isolating liner in said substrate,

applying a layer of a hard mask material to said surface of said substrate surrounding said isolating liner and copper interconnect member, and,

applying by electroless deposition with a precurser deposition of Pd particles a capping layer over said exposed copper interconnect member,

said capping layer being 50-300 Angstroms thick and having the properties of resistance to the diffusion of copper and the electromigration of copper.

4. The process of claim 3 wherein, in said step of applying a capping layer, said capping layer is an alloy of the A—

X—

Y type, where;

the ingredient A is a member of the group of Co and Ni,

the ingredient X is a member of the group of W, Sn and Si, and,

the ingredient Y is a member of the group of P and B.

5. The process of claim 4 wherein, in said step of applying a capping layer, said capping layer is an alloy taken from the group of CoWP and NiWP.

6. The process of claim 3 wherein, in said step of applying a layer of a hard mask material to said surface of said substrate, said hard mask material is a member of the group of Si3N4 and SiO2.

7. In the process of claim 3, following the step of applying said layer of hardmask material and before said step of applying said capping layer,

performing the additional step of planarizing to a common surface, by a technique selected from the group of chemical and mechanical polishing, the exposed interconnect member, the surrounding liner member and said hardmask layer.

8. The process of providing a multi integration layer copper interconnect interface in integrated circuit fabrication,

comprising the steps of:

first, positioning in a substrate, extending to and exposed at a surface thereon a copper interconnect member, surrounded by an electrically isolating liner in said substrate,

second, applying a layer of a hard mask material to said surface of said substrate surrounding said isolating liner and copper interconnect member,

third, planarizing to a common surface, by a technique selected from the group of chemical and mechanical polishing, the exposed interconnect member, the surrounding liner member and said hardmask layer,

fourth, applying a capping layer over said exposed copper interconnect member, said capping layer being 50-300 Angstroms thick and having the properties of resistance to the diffusion of copper and the electromigration of copper, and

repeating said first through fourth steps for each subsequent integration layer.