Semiconductor device and manufacturing method thereof

• US 6,573,607 B2
• Filed: 08/24/2001
• Issued: 06/03/2003
• Est. Priority Date: 08/31/1998
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Matsubara, Yoshihisa, Ito, Nobukazu
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Keshavan, Belur V
• Application Number:
  US09/939,396
• Publication Number:
  US 20020005587A1
• Time in Patent Office: 648 Days
• Field of Search: 257/762, 257/635, 257/758, 257/753, 257/752, 458/687, 458/618, 458/622, 458/635, 458/136, 458/672, 458/637
• US Class Current: 257/762
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/976 Temporary protective layer

Abstract

There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/min or less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.

Claims

1. A semiconductor device including multiple levels of copper interconnects;

wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide having a thickness of approximately 30 nm or more by an oxidation conducted at an oxidation rate of around 20 nm/min or less.

2. The semiconductor device according to claim 1, wherein said copper oxide on the surface of said underlying layer of copper comprises cupric oxide.

3. The semiconductor device according to claim 2, wherein said copper oxide is formed by applying an oxygen plasma treatment to the exposed surface of the underlying layer of copper interconnect.

4. The semiconductor device according to claim 3, wherein the copper oxide formed on the surface of said underlying copper interconnect is reduced to copper in a reductive atmosphere, at least at a contact part with another copper interconnect formed as an upper-level interconnect, prior to the formation of the upper-level copper interconnect.

5. The semiconductor device according to claim 2, wherein the copper oxide formed on the surface of said underlying copper interconnect is reduced to copper in a reductive atmosphere, at least at a contact part with another copper interconnect formed as an upper-level interconnect, prior to the formation of the upper-level copper interconnect.

6. The semiconductor device according to claim 1, wherein the copper oxide formed on the surface of said underlying copper interconnect is reduced to copper in a reductive atmosphere, at least at a contact part with another copper interconnect formed as an upper-level interconnect, prior to the formation of the upper-level copper interconnect.

7. A semiconductor device comprising:

a plurality of copper interconnect layers separated by a plurality of dielectric layers;

at least a selected one of the plurality of copper interconnect layers located below an uppermost one of the plurality of copper interconnect layers having a surface of the copper interconnect covered by a copper oxide layer with a thickness of about 30 nm or more;

a selected one of the plurality of dielectric layers disposed over the selected copper interconnect layer located below the uppermost copper interconnect layer includes at least one trench substantially containing at least one damascene copper interconnect line and a via hole making contact with a selected portion of the selected one of the copper interconnect layers that is located below uppermost copper interconnect layer;

at least that portion of the copper oxide layer exposed by the via hole is one of removed and reduced to copper to provide electrical contact between the uppermost copper interconnect layer and the selected one of the plurality of copper interconnect layers located below the uppermost one of the plurality of copper interconnect layers.

8. The semiconductor device according to claim 7, wherein said copper oxide comprises cupric oxide.

9. The semiconductor device according to claim 8, wherein said copper oxide layer is formed by an oxygen plasma treatment to the exposed surface of the copper interconnect layer.

10. The semiconductor device according to claim 9, wherein the oxygen plasma treatment temperature is in the range of about 25 to 150°

C.

11. The semiconductor device according to claim 9, wherein the plasma power at the is in the range of about 200 to 1000 W.

12. The semiconductor device according to claim 9, wherein copper oxide exposed by the via hole is reduced to copper in a reductive atmosphere.