Dual-lead type square semiconductor package and dual in-line memory module using the same

• US 6,573,611 B1
• Filed: 07/24/2000
• Issued: 06/03/2003
• Est. Priority Date: 11/24/1999
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Young Hee, Sohn, Hai Jeong, Jeon, Jun Young
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Andujar, Leonardo
• Application Number:
  US09/624,553
• Time in Patent Office: 1,044 Days
• Field of Search: 257/780, 257/787
• US Class Current: 257/780
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/1005 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/30107 Inductance

Abstract

Dual-lead type substantially square semiconductor packages and dual in-line memory modules using them are disclosed. The conventional memory module is internationally standardized, so it is hard to increase memory density by adding current packages to the module. The substantially square semiconductor packages provide improved and smaller packages in which a package length and a pin pitch are reduced, so that the memory density is increased without modifying a module size. The length of the leads are preferably substantially equal.

Claims

1. A semiconductor package comprising:

a package body including opposing first sides defining a body width and opposing second sides defining a body length, the package body being substantially square;

a semiconductor chip including a top surface and a plurality of bonding pads formed on the top surface, the plurality of bonding pads being arranged parallel to the opposing second sides on a central region of the top surface, the semiconductor chip being provided within the package body; and

a plurality of leads, each having an inner end and an outer end, the inner ends extending over the top surface of the semiconductor chip within the package body and electrically connecting to the bonding pads, the outer ends protruding from the package body along the opposing second sides,

wherein no leads protrude from the package body along the opposing first sides.

2. The semiconductor package of claim 1, wherein a length of each lead is substantially equal to a length of remaining leads of the plurality of leads.

3. The semiconductor package of claim 1, wherein the semiconductor package is a type of TSOP (Thin Small Outline Package).

4. The semiconductor package of claim 3, wherein the TSOP has fifty-four pins, a pin pitch of which is 0.4 ±

0.0 5 mm.

5. The semiconductor package of claim 4, wherein the body width is 10.16±

0.127 mm, the body length is 11.20±

0.127 mm, and a distance from the outer ends at one second side to the opposing outer ends at the other second side is 11.76±

0.2 mm.

6. The semiconductor package of claim 1, wherein the leads are copper.

7. The semiconductor package of claim 1, wherein a ratio of the body length to the body width of the package body ranges from substantially 0.9 to substantially 1.1.

8. A semiconductor package comprising:

a package body including opposing first sides having a first length and opposing second sides having a second length;

a semiconductor chip including a top surface and a plurality of bonding pads formed on the top surface, the plurality of bonding pads being arranged parallel to the opposing second sides on a central region of the top surface, the semiconductor chip being provided within the package body;

a plurality of leads, each having an inner lead and an outer lead, the inner leads extending over the top surface of the semiconductor chip within the package body, the outer leads protruding from the package body along the opposing second sides; and

a plurality of bond wires electrically connecting the plurality of leads to the plurality of bonding pads,

wherein the second length is longer than the first length and shorter than a distance from the outer leads at one of the second sides to the opposing outer leads at the other second side, and

wherein no leads protrude from the package body along the opposing first sides.

9. The semiconductor package of claim 8, wherein a length of each lead is substantially equal to a length of remaining leads of the plurality of leads.

10. The semiconductor package of claim 8, wherein the semiconductor package is a type of TSOP (Thin Small Outline Package).

11. The semiconductor package of claim 10, wherein the TSOP has fifty-four pins a pitch of which, i.e., a pitch between the adjacent outer leads, is 0.4±

0.05 mm.

12. The semiconductor package of claim 11, wherein the first length is 10.16±

0.127 mm, the second length is 11.20±

0.127 mm, and the distance from the outer leads at one second side to the opposing outer leads at the other second side is 11.76±

0.2 mm.

13. The semiconductor package of claim 8, wherein the leads are copper.

14. The semiconductor package of claim 8, wherein a ratio of the first length to the second length of the package body ranges from substantially 0.9 to substantially 1.0.

15. A memory module comprising:

a circuit substrate including upper and lower faces on each of which given circuit patterns are formed; and

a plurality of semiconductor packages, the semiconductor packages each having a package body including opposing first sides defining a body width and opposing second sides defining a body length, and outer leads protruding from the package body only along the opposing second sides, the package body being substantially square, said plurality of semiconductor packages being provided on the upper and lower faces and being electrically connected to the circuit patterns,

wherein the semiconductor packages on each face of the circuit substrate are arranged in at least two lengthwise rows and at least two widthwise rows.

16. The memory module of claim 15, wherein the memory module has a 1250±

6 mil width, a 2660±

6 mil length, and a 150 mil maximum thickness.

17. The memory module of claim 16, wherein each semiconductor package is a TSOP having fifty-four pins, a pin pitch of which is 0.4±

0.05 mm.

18. The memory module of claim 15, wherein the body width of each semiconductor package is 10.16±

0.127 mm, the body length of each semiconductor package is 11.20±

0.127 mm, and a distance from the-outer leads at one second side of the semiconductor package to the opposing outer leads at the other second side is 11.76±

0.2 mm.

19. The memory module of claim 15, wherein a ratio of the first length to the second length of each package body ranges from substantially 0.9 to substantially 1.1.

20. A memory module comprising:

a circuit substrate including upper and lower faces on each of which given circuit patterns are formed; and

a plurality of semiconductor packages, each semiconductor package comprising,

a package body including opposing first sides having a first length and opposing second sides having a second length;

a semiconductor chip including a top surface and a plurality of bonding pads formed on the top surface,

a plurality of leads, each having an inner lead and an outer lead, the inner leads extending over the top surface of the semiconductor chip within the package body, the outer leads protruding from the package body only along the opposing second sides, and

a plurality of bond wires electrically connecting the plurality of leads to the plurality of bonding pads,

wherein the second length is longer than the first length and shorter than a distance from the outer leads at one of the second sides to the opposing outer leads at the other second side, the plurality of semiconductor packages being provided on the upper and lower faces and electrically connected to the circuit patterns, and

wherein the packages on each face of the circuit substrate are arranged in at least two lengthwise rows and at least two widthwise rows.

21. The memory module of claim 20, wherein the memory module has a 1250±

6 mil width, a 2660±

6 mil length, and a 150 mil maximum thickness.

22. The memory module of claim 20, wherein each semiconductor package is a TSOP having fifty-four pins, a pin pitch of which is 0.4±

0.05 mm.

23. The memory module of claim 22, wherein the first length of each semiconductor package is 10.16±

0.127 mm, the second length of each semiconductor package is 11.20±

0.127 mm, and a distance from the outer leads at one second side of each semiconductor package to the opposing outer leads at the other second side is 11.76±

0.2 mm.