Circuit configuration for enabling a clock signal in a manner dependent on an enable signal
First Claim
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1. A circuit configuration for enabling a clock signal in a manner dependent on an enable signal, comprising:
- a first input terminal for receiving the clock signal;
a second input terminal for receiving the enable signal;
an output terminal providing an enabled clock signal;
a plurality of inverters;
a first logic combination element having input terminals and an output connected to said output terminal;
a first signal path having a delay element with an input side connected to said first input terminal and an output connected to said first logic combination element; and
a second signal path having an input side coupled to said first input terminal and to said second input terminal and an output connected to said first logic combination element, said second signal path containing second logic combination elements and a storage element having a set input and a reset input, said set input and said reset input connected to and being driven by said second logic combination elements, said second logic combination elements each having a first input connected to said first input terminal through an equal number of said inverters, said second logic combination elements each having a second input connected to said second input terminal through a different number of said inverters.
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Abstract
A circuit configuration for enabling a clock signal in a manner dependent on an enable signal has first and second signal paths that are fed to a NAND gate. The second signal path contains an RS flip-flop, upstream of which NAND gates are connected, which, for their part, are connected via different inverters to the input terminals for the clock signal and the enable signal, respectively.
47 Citations
6 Claims
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1. A circuit configuration for enabling a clock signal in a manner dependent on an enable signal, comprising:
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a first input terminal for receiving the clock signal;
a second input terminal for receiving the enable signal;
an output terminal providing an enabled clock signal;
a plurality of inverters;
a first logic combination element having input terminals and an output connected to said output terminal;
a first signal path having a delay element with an input side connected to said first input terminal and an output connected to said first logic combination element; and
a second signal path having an input side coupled to said first input terminal and to said second input terminal and an output connected to said first logic combination element, said second signal path containing second logic combination elements and a storage element having a set input and a reset input, said set input and said reset input connected to and being driven by said second logic combination elements, said second logic combination elements each having a first input connected to said first input terminal through an equal number of said inverters, said second logic combination elements each having a second input connected to said second input terminal through a different number of said inverters. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification
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Current AssigneePolaris Innovations Limited (Wi-LAN Inc.)
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Original AssigneeInfineon Technologies AG
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InventorsMenczigar, Ullrich, Heyne, Patrick
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Primary Examiner(s)LE, DON P
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Assistant Examiner(s)King, Doris
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Application NumberUS10/125,088Publication NumberTime in Patent Office411 DaysField of Search326/37, 326/46, 326/56-58, 326/82, 326/83, 326/96, 326/93, 326/95US Class Current326/93CPC Class CodesH03K 19/0016 by using a control or a clo...H03K 5/1252 Suppression or limitation o...
