Method and apparatus for variable length decoding and encoding of video streams

• US 6,573,846 B1
• Filed: 12/31/2001
• Issued: 06/03/2003
• Est. Priority Date: 12/31/2001
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Sarwar, Mushtaq A., Takahashi, Yutaka, Ouzilevski, Alexei V., Trivedi, Sushma Shrikant
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US10/038,797
• Time in Patent Office: 519 Days
• Field of Search: 341/67, 341/59, 341/63, 341/100, 341/101
• US Class Current: 341/67
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/321 Program or instruction counter, e.g. incrementing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: H03M 7/40 Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

Methods and apparatuses for decoding a compressed video stream. In one aspect of the invention, a method to decode a variable length encoded bit stream includes: concurrently processing first data obtained from variable length decoding a first code word in a register while variable length decoding a second code word in the register. In one example, processing the first data includes: looking up an inverse zigzag index; computing an Inverse Direct Cosine Transformation (IDCT) coefficient; storing the IDCT coefficient in a buffer in a transposed inverse zigzag order; and branching conditionally based on a condition encountered in variable length decoding the first code word.

Claims

1. A method to decode a variable length encoded bit stream, the method comprising:

concurrently processing first data obtained from variable length decoding a first code word in a register;

while variable length decoding a second code word in the register.

2. A method as in claim 1 wherein said processing first data comprises:

looking up an inverse zigzag index.

3. A method as in claim 2 wherein the inverse zigzag index is for storing an Inverse Direct Cosine Transformation (IDCT) coefficient in a transposed inverse zigzag order.

4. A method as in claim 1 wherein said processing first data comprises:

computing an Inverse Direct Cosine Transformation (IDCT) coefficient.

5. A method as in claim 4 wherein said processing first data further comprises:

storing the IDCT coefficient in a buffer in a transposed inverse zigzag order.

6. A method as in claim 1 wherein said processing first data comprises:

looking up a coefficient for inverse scaling.

7. A method as in claim 1 wherein said processing first data comprises:

branching conditionally based on a condition encountered in variable length decoding the first code word.

8. A method as in claim 7 wherein the condition is one of:

a) an end of block condition;

b) an adjust bit stream condition; and

c) an entry not found condition.

9. A method as in claim 1 wherein said variable length decoding the second code word is performed by an execution unit in response to receiving a single instruction.

10. A method as in claim 9 wherein, in response to the single instruction, the execution unit performs a method comprising:

receiving a string of bits;

generating a plurality of indices using a plurality of segments of bits in the string of bits;

looking up simultaneously a plurality of entries from a plurality of look-up tables using the plurality of indices; and

combining the plurality of entries into a first result.

11. A method as in claim 9 wherein the execution unit is one of a plurality of execution units of a Very Long Instruction Word (VLIW) processing engine.

12. A method to decode a variable length encoded bit stream on a processing engine having an instruction cache and local memory, the method comprising:

loading a first set of instructions into the instruction cache;

loading first data into the local memory;

generating second data from the first data by executing the first set of instructions;

loading the second data from the local memory into first memory external to the processing engine;

loading a second set of instructions into the instruction cache;

loading the second data from the first memory into the local memory; and

generating third data from the second data by executing the second set of instructions.

13. A method as in claim 12 wherein the first set of instructions comprises instructions for at least one of:

a) Macro Block Address Generation (MBAG); and

b) Variable Length Decoding (VLD).

14. A method as in claim 12 wherein the second set of instructions comprises instructions for at least one of:

a) Variable Length Decoding (VLD); and

b) Inverse Discrete Cosine Transformation (IDCT).

15. A method as in claim 12 wherein a second portion of the second data is generated concurrently while a first portion of the second data is loaded from the local memory into the first memory.

16. A method as in claim 12 wherein a first portion of the second data is generated concurrently from a first portion of the first data while a second portion of the first data is loaded from the first memory into the local memory.

17. A method as in claim 12 wherein a first portion of the third data is generated concurrently from a first portion of the second data while a second portion of the second data is loaded from the first memory into the local memory.

18. A method to decode a variable length encoded bit stream on a processing engine having local memory, the method comprising:

concurrently loading a first result generated from first data from the local memory into first memory external to the processing engine using a first at least one Direct Memory Access (DMA) channel;

while generating a second result from second data in the local memory; and

while loading third data into the local memory using a second at least one DMA channel.

19. A method as in claim 18 wherein:

the first, second, and third data are Inverse Direct Cosine Transformation (IDCT) coefficients; and

the first and second results are decompressed video streams.

20. A method as in claim 18 wherein, after a first portion of the first result is loaded into the first memory, a portion of the second result is stored into a location in the local memory in which the first portion of the first result is stored.

21. A method as in claim 18 wherein:

the first, second, and third data are compressed bit streams; and

the first and second results are Inverse Direct Cosine Transformation (IDCT) coefficients.

22. A method as in claim 18 wherein:

the first and second data are Inverse Direct Cosine Transformation (IDCT) coefficients;

the third data is a compressed bit stream; and

the first and second results are decompressed video streams.

23. A method as in claim 22 further comprising:

concurrently variable length decoding the third data to generate a first set of IDCT coefficients;

while loading the second result from the local memory into the first memory using the second at least one DMA channel.

24. A method as in claim 18 wherein the second result is stored into a location in the local memory in which the second data is stored.

25. A method to decode a variable length encoded bit stream, the method comprising:

concurrently executing a first set of instructions in a first processing engine to generate a first result from a first data for a bit stream;

while executing a second set of instructions in a second processing engine to generate a second result from a third result;

wherein the third result is generated from a second data for the bit stream in the first processing engine after execution of the first set of instructions.

26. A method as in claim 25 wherein the first set of instructions comprises instructions for at least one of:

a) Macro Block Address Generation (MBAG); and

b) Variable Length Decoding (VLD).

27. A method as in claim 25 wherein the second set of instructions comprises instructions for at least one of:

a) Variable Length Decoding (VLD); and

b) Inverse Discrete Cosine Transformation (IDCT).

28. A method to decode a variable length encoded bit stream, the method comprising:

variable length decoding a bit stream until a condition in a set of conditions is encountered;

constructing first data containing information about a segment of the bit stream which has not been decoded; and

storing first data in a location in memory, the location being independent on the condition.

29. A method as in claim 28 wherein the set of conditions comprises:

a) an end of block condition; and

b) an adjust bit stream condition.

30. A method as in claim 28 wherein the first data comprises:

a) bits in the segment;

b) a bit length of the segment; and

c) a type of the segment.

31. A method as in claim 30 wherein the type of the segment is one of:

a) incomplete code bits; and

b) remaining bits.

32. A machine readable media containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to decode a variable length encoded bit stream, the method comprising:

concurrently processing first data obtained from variable length decoding a first code word in a register;

while variable length decoding a second code word in the register.

33. A media as in claim 32 wherein said processing first data comprises:

looking up an inverse zigzag index.

34. A media as in claim 33 wherein the inverse zigzag index is for storing an Inverse Direct Cosine Transformation (IDCT) coefficient in a transposed inverse zigzag order.

35. A media as in claim 32 wherein said processing first data comprises:

computing an Inverse Direct Cosine Transformation (IDCT) coefficient.

36. A media as in claim 35 wherein said processing first data further comprises:

storing the IDCT coefficient in a buffer in a transposed inverse zigzag order.

37. A media as in claim 32 wherein said processing first data comprises:

looking up a coefficient for inverse scaling.

38. A media as in claim 32 wherein said processing first data comprises:

branching conditionally based on a condition encountered in variable length decoding the first code word.

39. A media as in claim 38 wherein the condition is one of:

a) an end of block condition;

b) an adjust bit stream condition; and

c) an entry not found condition.

40. A media as in claim 32 wherein said variable length decoding the second code word is performed by an execution unit in response to receiving a single instruction.

41. A media as in claim 40 wherein, in response to the single instruction, the execution unit performs a method comprising:

receiving a string of bits;

generating a plurality of indices using a plurality of segments of bits in the string of bits;

looking up simultaneously a plurality of entries from a plurality of look-up tables using the plurality of indices; and

combining the plurality of entries into a first result.

42. A media as in claim 40 wherein the execution unit is one of a plurality of execution units of a Very Long Instruction Word (VLIW) processing engine.

43. A machine readable media containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to decode a variable length encoded bit stream on a processing engine having an instruction cache and local memory, the method comprising:

loading a first set of instructions into the instruction cache;

loading first data into the local memory;

generating second data from the first data by executing the first set of instructions;

loading the second data from the local memory into first memory external to the processing engine;

loading a second set of instructions into the instruction cache;

loading the second data from the first memory into the local memory; and

generating third data from the second data by executing the second set of instructions.

44. A media as in claim 43 wherein the first set of instructions comprises instructions for at least one of:

a) Macro Block Address Generation (MBAG); and

b) Variable Length Decoding (VLD).

45. A media as in claim 43 wherein the second set of instructions comprises instructions for at least one of:

a) Variable Length Decoding (VLD); and

b) Inverse Discrete Cosine Transformation (IDCT).

46. A media as in claim 43 wherein a second portion of the second data is generated concurrently while a first portion of the second data is loaded from the local memory into the first memory.

47. A media as in claim 43 wherein a first portion of the second data is generated concurrently from a first portion of the first data while a second portion of the first data is loaded from the first memory into the local memory.

48. A media as in claim 43 wherein a first portion of the third data is generated concurrently from a first portion of the second data while a second portion of the second data is loaded from the first memory into the local memory.

49. A machine readable media containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to decode a variable length encoded bit stream on a processing engine having local memory, the method comprising

concurrently loading a first result generated from first data from the local memory into first memory external to the processing engine using a first at least one Direct Memory Access (DMA) channel;

while generating a second result from second data in the local memory; and

while loading third data into the local memory using a second at least one DMA channel.

50. A media as in claim 49 wherein:

the first, second, and third data are Inverse Direct Cosine Transformation (IDCT) coefficients; and

the first and second results are decompressed video streams.

51. A media as in claim 49 wherein, after a first portion of the first result is loaded into the first memory, a portion of the second result is stored into a location in the local memory in which the first portion of the first result is stored.

52. A media as in claim 49 wherein:

the first, second, and third data are compressed bit streams; and

the first and second results are Inverse Direct Cosine Transformation (IDCT) coefficients.

53. A media as in claim 49 wherein:

the first and second data are Inverse Direct Cosine Transformation (IDCT) coefficients;

the third data is a compressed bit stream; and

the first and second results are decompressed video streams.

54. A media as in claim 53 wherein the method further comprises:

concurrently variable length decoding the third data to generate a first set of IDCT coefficients;

while loading the second result from the local memory into the first memory using the second at least one DMA channel.

55. A media as in claim 49 wherein the second result is stored into a location in the local memory in which the second data is stored.

56. A machine readable media containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to decode a variable length encoded bit stream, the method comprising:

concurrently executing a first set of instructions in a first processing engine to generate a first result from a first data for a bit stream;

while executing a second set of instructions in a second processing engine to generate a second result from a third result;

wherein the third result is generated from a second data for the bit stream in the first processing engine after execution of the first set of instructions.

57. A media as in claim 56 wherein the first set of instructions comprises instructions for at least one of:

a) Macro Block Address Generation (MBAG); and

b) Variable Length Decoding (VLD).

58. A media as in claim 56 wherein the second set of instructions comprises instructions for at least one of:

a) Variable Length Decoding (VLD); and

b) Inverse Discrete Cosine Transformation (IDCT).

59. A machine readable media containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to decode a variable length encoded bit stream, the method comprising:

variable length decoding a bit stream until a condition in a set of conditions is encountered;

constructing first data containing information about a segment of the bit stream which has not been decoded; and

storing first data in a location in memory, the location being independent on the condition.

60. A media as in claim 59 wherein the set of conditions comprises:

a) an end of block condition; and

b) an adjust bit stream condition.

61. A media as in claim 59 wherein the first data comprises:

a) bits in the segment;

b) a bit length of the segment; and

c) a type of the segment.

62. A media as in claim 61 wherein the type of the segment is one of:

a) incomplete code bits; and

b) remaining bits.

63. A variable length encoded bit stream decoder comprising:

means for processing first data obtained from variable length decoding a first code word in a register; and

means for variable length decoding a second code word in the register;

wherein the above means operate concurrently.

64. A decoder as in claim 63 wherein said means for processing first data comprises:

means for looking up an inverse zigzag index.

65. A decoder as in claim 64 wherein the inverse zigzag index is for storing an Inverse Direct Cosine Transformation (IDCT) coefficient in a transposed inverse zigzag order.

66. A decoder as in claim 63 wherein said means for processing first data comprises:

means for computing an Inverse Direct Cosine Transformation (IDCT) coefficient.

67. A decoder as in claim 66 wherein said means for processing first data further comprises:

means for storing the IDCT coefficient in a buffer in a transposed inverse zigzag order.

68. A decoder as in claim 63 wherein said means for processing first data comprises:

means for looking up a coefficient for inverse scaling.

69. A decoder as in claim 63 wherein said means for processing first data comprises:

means for branching conditionally based on a condition encountered in variable length decoding the first code word.

70. A decoder as in claim 69 wherein the condition is one of:

a) an end of block condition;

b) an adjust bit stream condition; and

c) an entry not found condition.

71. A decoder as in claim 63 wherein said variable length decoding the second code word is performed by an execution unit in response to receiving a single instruction.

72. A decoder as in claim 71 wherein the execution unit comprises:

means for receiving a string of bits;

means for generating a plurality of indices using a plurality of segments of bits in the string of bits;

means for looking up simultaneously a plurality of entries from a plurality of look-up tables using the plurality of indices; and

means for combining the plurality of entries into a first result;

wherein the above means operate in response to receiving a single instruction.

73. A decoder as in claim 71 wherein the execution unit is one of a plurality of execution units of a Very Long Instruction Word (VLIW) processing engine.

74. A variable length encoded bit stream decoder comprising:

a processing engine having an instruction cache and local memory;

means for loading a first set of instructions into the instruction cache;

means for loading first data into the local memory;

means for generating second data from the first data by executing the first set of instructions;

means for loading the second data from the local memory into first memory external to the processing engine;

means for loading a second set of instructions into the instruction cache;

means for loading the second data from the first memory into the local memory; and

means for generating third data from the second data by executing the second set of instructions.

75. A decode as in claim 74 wherein the first set of instructions comprises instructions for at least one of:

a) Macro Block Address Generation (MBAG); and

b) Variable Length Decoding (VLD).

76. A decode as in claim 74 wherein the second set of instructions comprises instructions for at least one of:

a) Variable Length Decoding (VLD); and

b) Inverse Discrete Cosine Transformation (IDCT).

77. A decode as in claim 74 wherein a second portion of the second data is generated concurrently while a first portion of the second data is loaded from the local memory into the first memory.

78. A decode as in claim 74 wherein a first portion of the second data is generated concurrently from a first portion of the first data while a second portion of the first data is loaded from the first memory into the local memory.

79. A decode as in claim 74 wherein a first portion of the third data is generated concurrently from a first portion of the second data while a second portion of the second data is loaded from the first memory into the local memory.

80. A variable length encoded bit stream decoder comprising:

a processing engine having local memory;

means for loading a first result generated from first data from the local memory into first memory external to the processing engine using a first at least one Direct Memory Access (DMA) channel;

means for generating a second result from second data in the local memory; and

means for loading third data into the local memory using a second at least one DMA channel;

wherein the above means operate concurrently.

81. A decode as in claim 80 wherein:

the first, second, and third data are Inverse Direct Cosine Transformation (IDCT) coefficients; and

the first and second results are decompressed video streams.

82. A decode as in claim 80 wherein, after a first portion of the first result is loaded into the first memory, a portion of the second result is stored into a location in the local memory in which the first portion of the first result is stored.

83. A decode as in claim 80 wherein:

the first, second, and third data are compressed bit streams; and

the first and second results are Inverse Direct Cosine Transformation (IDCT) coefficients.

84. A decode as in claim 80 wherein:

the first and second data are Inverse Direct Cosine Transformation (IDCT) coefficients;

the third data is a compressed bit stream; and

the first and second results are decompressed video streams.

85. A decode as in claim 84 further comprising:

means for variable length decoding the third data to generate a first set of IDCT coefficients; and

means for loading the second result from the local memory into the first memory using the second at least one DMA channel;

wherein the above means operates concurrently.

86. A decode as in claim 80 wherein the second result is stored into a location in the local memory in which the second data is stored.

87. A variable length encoded bit stream decoder comprising:

means for generating a first result from a first data for a bit stream in a first processing engine by executing a first set of instructions;

means for generating a second result from a third result in a second processing engine by executing a second set of instructions;

wherein the above means operate concurrently; and

wherein the third result is generated from a second data for the bit stream in the first processing engine after execution the first set of instructions.

88. A decode as in claim 87 wherein the first set of instructions comprises instructions for at least one of:

a) Macro Block Address Generation (MBAG); and

b) Variable Length Decoding (VLD).

89. A decode as in claim 87 wherein the second set of instructions comprises instructions for at least one of:

a) Variable Length Decoding (VLD); and

b) Inverse Discrete Cosine Transformation (IDCT).

90. A variable length encoded bit stream decoder comprising:

means for variable length decoding a bit stream until a condition in a set of conditions is encountered;

means for constructing first data containing information about a segment of the bit stream which has not been decoded; and

means for storing first data in a location in memory, the location being independent on the condition.

91. A decode as in claim 90 wherein the set of conditions comprises:

a) an end of block condition; and

b) an adjust bit stream condition.

92. A decode as in claim 90 wherein the first data comprises:

a) bits in the segment;

b) a bit length of the segment; and

c) a type of the segment.

93. A decode as in claim 92 wherein the type of the segment is one of:

a) incomplete code bits; and

b) remaining bits.

94. A variable length encoded bit stream decoder comprising:

memory;

a register; and

a first execution unit and a plurality of other execution units coupled to the register and the memory, the plurality of other execution units concurrently processing first data obtained from variable length decoding a first code word in the register while the first execution unit variable length decoding a second code word in the register.

95. A decoder as in claim 94 wherein, in processing the first data, the plurality of other execution units look up an inverse zigzag index.

96. A decoder as in claim 95 wherein the inverse zigzag index is for storing an Inverse Direct Cosine Transformation (IDCT) coefficient in a transposed inverse zigzag order.

97. A decoder as in claim 94 wherein, in processing the first data, the plurality of other execution units compute an Inverse Direct Cosine Transformation (IDCT) coefficient.

98. A decoder as in claim 97 wherein, in processing the first data, the plurality of other execution units further store the IDCT coefficient in the memory in a transposed inverse zigzag order.

99. A decoder as in claim 94 wherein, in processing the first data, the plurality of other execution units look up a coefficient for inverse scaling.

100. A decoder as in claim 94 wherein, in processing the first data, the plurality of other execution units branch conditionally based on a condition encountered in variable length decoding the first code word.

101. A decoder as in claim 100 wherein the condition is one of:

a) an end of block condition;

b) an adjust bit stream condition; and

c) an entry not found condition.

102. A decoder as in claim 94 wherein the first execution unit variable length decodes the second code word in response to receiving a single instruction.

103. A decoder as in claim 102 wherein the first execution unit comprises:

a plurality of look-up tables;

a first circuit coupled to the plurality of look-up tables, the first circuit configured to receive a string of bits; and

a second circuit coupled to the plurality of look-up tables and the first circuit, the second circuit configured to receive a plurality of data elements, in response to the microprocessor receiving a single instruction,

the second circuit generating a plurality of indices using the plurality of data elements and the string of bits,

the plurality of look-up tables looking up simultaneously a plurality of entries using the plurality of indices; and

a third circuit coupled to the plurality of look-up tables, the third circuit combining the plurality of values into a first result.

104. A decoder as in claim 102 wherein the first execution unit and the plurality of other execution units are configured to process Very Long Instruction Words (VLIW).

105. A variable length encoded bit stream decoder comprising:

first memory;

a processing engine coupled to the first memory, the processing engine comprising an instruction cache, local memory and a plurality of execution units;

the processing engine loading a first set of instructions into the instruction cache, loading first data into the local memory, generating second data from the first data by executing the first set of instructions using the plurality of execution units, loading the second data from the local memory into the first memory, loading a second set of instructions into the instruction cache, loading the second data from the first memory into the local memory, and generating third data from the second data by executing the second set of instructions using the plurality of execution units.

106. A decode as in claim 105 wherein the first set of instructions comprises instructions for at least one of:

a) Macro Block Address Generation (MBAG); and

b) Variable Length Decoding (VLD).

107. A decode as in claim 105 wherein the second set of instructions comprises instructions for at least one of:

a) Variable Length Decoding (VLD); and

b) Inverse Discrete Cosine Transformation (IDCT).

108. A decode as in claim 105 wherein a second portion of the second data is generated concurrently while a first portion of the second data is loaded from the local memory into the first memory.

109. A decode as in claim 105 wherein a first portion of the second data is generated concurrently from a first portion of the first data while a second portion of the first data is loaded from the first memory into the local memory.

110. A decode as in claim 105 wherein a first portion of the third data is generated concurrently from a first portion of the second data while a second portion of the second data is loaded from the first memory into the local memory.

111. A variable length encoded bit stream decoder comprising:

a processing engine comprising local memory, a first at least one Direct Memory Access (DMA) channel, a second at least one DMA channel, and a plurality of execution units; and

first memory coupled to the processing engine, the first at least one DMA channel concurrently loading a first result generated from first data from the local memory into the first memory, while the plurality of execution units generating a second result from second data in the local memory, and while the second at least one DMA channel loading third data into the local memory.

112. A decode as in claim 111 wherein:

the first, second, and third data are Inverse Direct Cosine Transformation (IDCT) coefficients; and

the first and second results are decompressed video streams.

113. A decode as in claim 111 wherein, after a first portion of the first result is loaded into the first memory, a portion of the second result is stored into a location in the local memory in which the first portion of the first result is stored.

114. A decode as in claim 111 wherein:

the first, second, and third data are compressed bit streams; and

the first and second results are Inverse Direct Cosine Transformation (IDCT) coefficients.

115. A decode as in claim 111 wherein:

the first and second data are Inverse Direct Cosine Transformation (IDCT) coefficients;

the third data is a compressed bit stream; and

the first and second results are decompressed video streams.

116. A decode as in claim 115 wherein the plurality of execution units concurrently variable length decode the third data to generate a first set of IDCT coefficients, while the second at least one DMA channel loads the second result from the local memory into the first memory.

117. A decode as in claim 111 wherein the second result is stored into a location in the local memory in which the second data is stored.

118. A variable length encoded bit stream decoder comprising:

a first processing engine;

a second processing engine coupled to the first processing engine, the first processing engine concurrently executing a first set of instructions to generate a first result from a first data for a bit stream, while the second processing engine executing a second set of instructions to generate a second result from the first result;

wherein the third result is generated from a second data for the bit stream by the first processing engine after executing the first set of instructions.

119. A decode as in claim 118 wherein the first set of instructions comprises instructions for at least one of:

a) Macro Block Address Generation (MBAG); and

b) Variable Length Decoding (VLD).

120. A decode as in claim 118 wherein the second set of instructions comprises instructions for at least one of:

a) Variable Length Decoding (VLD); and

b) Inverse Discrete Cosine Transformation (IDCT).

121. A variable length encoded bit stream decoder comprising:

a processor;

memory coupled to the processor, the processor variable length decoding a bit stream until a condition in a set of conditions is encountered, the processor constructing first data containing information about a segment of the bit stream which has not been decoded, and the processor storing first data in a location in the memory, wherein the location is independent on the condition.

122. A decode as in claim 121 wherein the set of conditions comprises:

a) an end of block condition; and

b) an adjust bit stream condition.

123. A decode as in claim 121 wherein the first data comprises:

a) bits in the segment;

b) a bit length of the segment; and

c) a type of the segment.

124. A decode as in claim 123 wherein the type of the segment is one of:

a) incomplete code bits; and

b) remaining bits.