Method and apparatus for providing a single-instruction multiple data digital camera system that integrates on-chip sensing and parallel processing

• US 6,573,936 B2
• Filed: 08/17/1998
• Issued: 06/03/2003
• Est. Priority Date: 08/17/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Korta, Jean-Charles W., Afghahi, Cyrus M., Connolly, Kevin M., Morris, Tonia G.
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): NGUYEN, LUONG TRUNG
• Application Number:
  US09/135,130
• Publication Number:
  US 20030058345A1
• Time in Patent Office: 1,751 Days
• Field of Search: 348/294, 348/298, 348/302, 348/308, 348/241, 382/218, 345/100
• US Class Current: 348/294
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A single-chip digital camera system is described. In one embodiment, the single-chip digital camera system includes a sensor array including rows and columns of discrete sensor elements, corresponding analog-to-digital converters to convert analog values into digital data, a storage element coupled to the analog-to-digital converters, to store the digital data, and a plurality of arithmetic logic units coupled to the storage element, to operate on the digital data. The digital camera system also includes a switching matrix Which is coupled between the array of analog-to-digital converters and the memory element. The switching matrix spatially rotates the analog-to-digital converter outputs for storing such outputs in the memory element.

Claims

1. A digital camera system comprising:

a sensor array that comprises at least two sensor sub-arrays including discrete sensor elements;

analog-to-digital converters to convert analog values into digital data, each coupled to a corresponding sensor sub-array;

a storage element coupled to the analog-to-digital converters; and

a switching matrix coupled to the storage element to provide spatial rotation of the digital data, the switching matrix comprises an array of driving elements each driving element including a select transistor and a driving transistor.

2. The digital camera system of claim 1 further comprising a memory element coupled to the switching matrix.

3. The digital camera system of claim 2, wherein the storage element includes a plurality of digital storage elements corresponding to the analog-to-digital converters and being implemented to fit within a pitch of a column.

4. The digital camera system of claim 1 further comprising a plurality of arithmetic logic units coupled to the storage element.

5. The digital camera system of claim 2, wherein the switching matrix further includes a plurality of column lines, each uniquely coupled to one of a plurality of row lines so that the driving elements of a row are coupled to one of the plurality of column lines.

6. The digital camera system of claim 4 wherein each arithmetic logic unit is coupled to adjacent arithmetic logic units to pass data therebetween.

7. The digital camera system of claim 4 further comprising a first-in first-out device coupled to receive the output of one or more arithmetic logic units.

8. The digital camera system of claim 7 further comprising an input/output interface coupled to at least the first-in first out device.

23. The digital camera system of claim 2 being integrated on a single integrated circuit chip.

9. A digital camera system, comprising:

a plurality of block-columns, each including,

rows and columns of pixel sensor elements, the pixel sensor elements to capture an image and provide a signal representation thereof,

analog-to-digital converters, each coupled to a corresponding column of sensor elements, each analog-to-digital converter to provide a digital value, responsive to the outputs of the sensor elements,

a switching matrix coupled to the analog-to-digital converters, the switching matrix to provide spatial rotation of the digital data, the switching matrix including an array of driving elements each driving element including a select transistor and a driving transistor, and

an arithmetic logic unit coupled to the switching matrix.

10. The digital camera system of claim 9 wherein each block-column further comprises a memory element coupled to the switching matrix and the arithmetic logic unit, the memory element to receive the spatially rotated digital data from the switching matrix.

11. The digital camera system of claim 9 wherein the analog-to-digital converters for each block-column further comprise a first storage element including storage registers coupled to receive the digital data from the switching matrix, the storage registers being implemented to fit within a pitch of a column.

12. The digital camera system of claim 11 wherein each storage register corresponds to one of the analog-to-digital converters.

13. The digital camera system of claim 9 wherein the pixel sensor elements are complementary metal-oxide semiconductor elements.

14. The digital camera system of claim 10 wherein the arithmetic logic unit in each block-column is coupled to arithmetic logic units in adjacent block-columns to pass data therebetween.

15. The digital camera system of claim 10 wherein each block-column further comprises a first-in first-out device coupled to receive an output of the arithmetic logic unit.

16. The digital camera system of claim 10 wherein each block-column further comprises a second memory element and a second arithmetic logic unit.

17. The digital camera system of claim 16 wherein the arithmetic logic units of a first set of adjacent block-columns are coupled together and the second arithmetic logic units of a second set of adjacent block-columns are coupled together, wherein the first and second sets of adjacent block-columns are different.

18. The digital camera system of claim 9 further comprising control circuitry, said control circuitry to control the block-columns in parallel.

24. The digital camera system of claim 9 being integrated on a single integrated circuit chip.

19. A method, comprising:

providing rows and columns of discrete sensor elements, to capture an image and provide an analog representation thereof;

converting the analog representations corresponding to each column into digital values;

spatial rotating the digital values through an array of driving elements each including a select transistor and a driving transistor;

storing the rotated digital values; and

operating on the rotated digital values in parallel to provide an output image.

20. A digital camera system, comprising:

a sensor array including rows and columns of discrete sensor elements;

analog-to-digital converter means coupled to a corresponding column of sensor elements, for converting analog values into digital data;

storage means coupled to the analog-to-digital converter means, for storing the digital data;

switching means coupled to the storage means for spatially rotating the digital data, the switching means including an array of driving elements each driving element including a select transistor and a driving transistor; and

first arithmetic logic unit means for performing operations on the spatially rotated digital data.

21. The digital camera system of claim 20, wherein the storage means being implemented to fit within a pitch of a column.

22. The digital camera system of claim 20 wherein the first arithmetic logic unit means is coupled to an adjacent second arithmetic logic unit means for transferring data therebetween.

25. The digital camera system of claim 21 being integrated on a single integrated circuit chip.