Hybrid circuit having nanotube electromechanical memory

• US 6,574,130 B2
• Filed: 07/25/2001
• Issued: 06/03/2003
• Est. Priority Date: 07/25/2001
• Status: Expired due to Term

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: Brock, Darren K., Segal, Brent M., Rueckes, Thomas
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/915,095
• Publication Number:
  US 20030021141A1
• Time in Patent Office: 678 Days
• Field of Search: 365/151, 365/129
• US Class Current: 365/129
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/81 Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
• CPC Class Codes: G11C 23/00 Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor
• CPC Class Codes: Y10S 977/724 Devices having flexible or movable element
• CPC Class Codes: Y10S 977/734 Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/942 including protein logic element
• CPC Class Codes: Y10S 977/943 Information storage or retrieval using nanostructure

Abstract

A hybrid memory system having electromechanical memory cells is disclosed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.

Claims

1. A hybrid memory system, comprising:

a memory cell core circuit having an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon;

an access circuit for providing array addresses to the memory cell core circuit to select at least one corresponding cell, the access circuit being constructed of semiconductor circuit elements.

2. The hybrid memory system of claim 1 wherein the memory cell core circuit further includes a first and second decoder, the first decoder being responsive to the array addresses to select a row of cells within the array, and the second decoder being responsive to the array addresses to select at least one column of cells in the array.

3. The hybrid circuit of claim 1 wherein the memory cell core circuit is constructed as a first individual integrated circuit chip and wherein the access circuit is not included in said chip.

4. The hybrid circuit of claim 1 wherein the memory cell core circuit is constructed as a first individual integrated circuit chip and wherein the access circuit is a second integrated circuit chip in communication with the first chip.

5. The hybrid circuit of claim 1 wherein the access circuit further provides a PCI bus interface.

6. The hybrid circuit of claim 2 wherein the first and second decoders are constructed with crossbar junctions, one element of which is a nanotube or a nanotube ribbon.