Dual bit line driver for memory

• US 6,574,148 B2
• Filed: 07/12/2001
• Issued: 06/03/2003
• Est. Priority Date: 07/12/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chevallier, Christophe
• Primary Examiner(s): Lam, David
• Application Number:
  US09/904,233
• Publication Number:
  US 20030012053A1
• Time in Patent Office: 691 Days
• Field of Search: 365/185.23, 365/185.33, 365/230.06, 365/189.04, 365/189.01, 365/185.26, 365/190
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A non-volatile memory device has memory cells arranged in addressable columns. The memory cells in each column are coupled to a common bit line. Bit line driver circuitry coupled to the bit line includes multiple drivers. In one embodiment, two drivers are coupled to opposite ends of the bit line. The driver circuits can be activated together, or separately, in response to decoder circuitry. The memory device can be a flash memory device having floating gate memory cells.

Claims

1. A memory device comprising:

an array of voltage programmable memory cells;

a bit line coupled to a portion of the memory cells; and

first and second driver circuits respectively coupled to first and second end regions of the bit line.

2. The memory device of claim 1 wherein the memory cells are non-volatile.

3. A memory device comprising:

an array of memory cells;

a bit line coupled to a portion of the memory cells; and

first and second driver circuits respectively coupled to first and second end regions of the bit line, further comprising a decoder circuit to selectively activate the first and second driver circuits.

4. The memory device of claim 3 wherein the decoder circuit selectively activates either the first or second driver circuit independently.

5. The memory device of claim 4 wherein the decoder circuit selectively activates either the first or second driver circuit based upon a location of a memory cell being programmed.

6. A flash memory device comprising:

an array of floating gate non-volatile memory cells arranged in rows and columns;

a bit line coupled to a portion of the non-volatile memory cells;

first and second driver circuits respectively coupled to first and second end regions of the bit line; and

a decoder circuit to selectively activate the first and second driver circuits.

7. The flash memory device of claim 6 further comprising address input connections to receive externally provided address signals, wherein the decoder circuit selectively activates the first and second driver circuits in response to the address signals.

8. The flash memory device of claim 6 wherein the decoder circuit selectively activates either the first or second driver circuit independently.

9. A method of programming a non-volatile memory comprising:

selecting a first non-volatile memory cell;

identifying a bit line coupled to the first non-volatile memory cell; and

activating either a first or second bit line driver coupled to the identified bit line.

10. The method of claim 9 wherein selecting the first non-volatile memory cell comprises receiving externally provided address signals.

11. The method of claim 10 wherein identifying the bit line comprises decoding the address signals using a decoder circuit.

12. The method of claim 11 wherein the first or second bit line driver is activated by the decoder circuit.

13. The method of claim 9 wherein the first and second bit line drivers are activated simultaneously.

14. A non-volatile memory device comprising:

an array of non-volatile voltage programmable memory cells arranged in rows and columns;

a bit line having a resistance of R and coupled to a portion of the non-volatile memory cells; and

X distributed driver circuits coupled to the bit line, such that a resistance between each of the non-volatile memory cells and any of the driver circuits is less than R/X, wherein X is two or more.

19. The non-volatile memory device of claim 14 wherein X equals two and the two distributed driver circuits are located at opposite ends of the bit line.

15. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows and columns;

a bit line having a resistance of R and coupled to a portion of the non-volatile memory cells; and

X distributed driver circuits coupled to the bit line, such that a resistance between each of the non-volatile memory cells and any of the driver circuits is less than R/X, wherein X is two or more, further comprising a decoder circuit to selectively activate the X distributed driver circuits.

16. The non-volatile memory device of claim 15 wherein the decoder circuit selectively activates the X distributed driver circuits independently such that only one driver circuit is activated at a time.

17. The non-volatile memory device of claim 15 wherein the decoder circuit selectively simultaneously activates the X distributed driver circuits.

18. The non-volatile memory device of claim 15 wherein the decoder circuit selectively activates the X distributed driver circuits in response to an externally provided array address.

20. A method of programming a flash memory comprising:

initiating a program operation on a first floating gate transistor memory cell;

identifying a bit line coupled to a drain region of the first floating gate transistor memory cell;

activating at least one of a plurality of distributed bit line drivers coupled to the identified bit line;

generating a bit line program voltage with the activated one of the plurality of distributed bit line drivers; and

coupling the bit line program voltage to the first floating gate transistor memory cell.

21. The method of claim 20 wherein activating at least one of the plurality of distributed bit line drivers comprises simultaneously activating first and second ones of the plurality of distributed bit line drivers.

22. The method of claim 20 wherein un-activated ones of the plurality of distributed bit line drivers are placed in a tri-state condition.

23. A method of programming a flash memory comprising:

initiating a program operation on a first floating gate transistor memory cell;

identifying a bit line coupled to a drain region of the first floating gate transistor memory cell;

activating a plurality of distributed bit line drivers coupled to the identified bit line;

generating a bit line program voltage with the plurality of distributed bit line drivers; and

coupling the bit line program voltage to the first floating gate transistor memory cell.

24. A flash memory system comprising:

an external processor; and

a flash memory coupled to the external processor comprising,

an array of floating gate non-volatile memory cells arranged in rows and columns,

a bit line coupled to a column of the non-volatile memory cells,

first and second driver circuits respectively coupled to first and second end regions of the bit line, and

a decoder circuit to selectively activate the first and second driver circuits.

25. The flash memory system of claim 24 wherein the flash memory further comprising address input connections to receive externally provided address signals, wherein the decoder circuit selectively activates the first and second driver circuits in response to the address signals.

26. The flash memory system of claim 24 wherein the decoder circuit selectively activates either the first or second driver circuit independently.

27. A non-volatile memory device comprising:

an array of non-volatile voltage programmable memory cells arranged in rows and columns;

a bit line having a resistance of R and coupled to the non-volatile memory cells; and

X distributed driver circuits coupled to the bit line, wherein first and second ones of the X distributed driver circuits are coupled to opposite ends of the bit line, and a resistance between each of the non-volatile memory cells and any of the driver circuits is less than R/2(X−

1).

28. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows and columns;

a bit line having a resistance of R and coupled to the non-volatile memory cells; and

X distributed driver circuits coupled to the bit line, wherein first and second ones of the X distributed driver circuits are coupled to opposite ends of the bit line, and a resistance between each of the non-volatile memory cells and any of the driver circuits is less than R/2(X−

1), further comprising a decoder circuit to selectively activate the X distributed driver circuits.

29. The non-volatile memory device of claim 28 wherein the decoder circuit selectively activates the X distributed driver circuits independently such that only one driver circuit is activated at a once.

30. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows and columns;

a bit line having a resistance of R and coupled to the non-volatile memory cells; and

X distributed driver circuits coupled to the bit line, wherein first and second ones of the X distributed driver circuits are coupled to opposite ends of the bit line, and a resistance between each of the non-volatile memory cells and any of the driver circuits is less than R/2(X−

1), wherein all of the distributed driver circuits can be simultaneously activated.

31. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows and columns;

a bit line having a resistance of R and coupled to the non-volatile memory cells; and

X distributed driver circuits coupled to the bit line, wherein first and second ones of the X distributed driver circuits are coupled to opposite ends of the bit line, and a resistance between each of the non-volatile memory cells and any of the driver circuits is less than R/2(X−

1), wherein all of the distributed driver circuits can be simultaneously activated and wherein an equivalent resistance between the distributed driver circuits and any of the non-volatile memory cells is less than R/(4*(X−

1)) when all of the distributed driver circuits are simultaneously activated.