High-data-rate supplemental channel for CDMA telecommunications system

• US 6,574,210 B2
• Filed: 08/06/2001
• Issued: 06/03/2003
• Est. Priority Date: 01/15/1997
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Tiedemann, Edward G. Jr., Jou, Yu-Cheun, Odenwalder, Joseph P., Antonio, Franklin P.
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): PHAN, MAN U
• Application Number:
  US09/924,336
• Publication Number:
  US 20020009063A1
• Time in Patent Office: 666 Days
• Field of Search: 370/206, 370/209, 370/335, 370/342, 370/468, 370/320, 375/142, 375/150, 375/309, 375/200, 375/208, 375/209, 375/260
• US Class Current: 370/342
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 7/264 for data rate control
• CPC Class Codes: H04J 13/0003 Code application, i.e. aspects relating to how codes are applied to form multiplexed channels
• CPC Class Codes: H04J 13/0048 Walsh
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/0067 Rate matching H04L1/0013 and H04L1/08 take precedence
• CPC Class Codes: H04L 1/08 by repeating transmission, e.g. Verdan system H04L1/1858 and H04L1/189 take precedence
• CPC Class Codes: H04L 2001/0093 Point-to-multipoint

Abstract

A novel and improved method for implementing a high-transmission-rate over-the-air interface is described. A transmit system provides an in-phase channel set and a quadrature-phase channel set. The in-phase channel set is used to provide a complete set of orthogonal medium rate control and traffic channels. The quadrature-phase channel set is used to provide a high-rate supplemental channel and an extended set of medium rate channels that are orthogonal to each other and the original medium rate channels. The high-rate supplemental channel is generated over a set of medium rate channels using a short channel code. The medium rate channel are generated using a set of long channel codes.

Claims

1. An digital signal processing apparatus, comprising:

a memory means for retaining information;

a digital signal processing means communicatively engageable with said memory means, the digital signal processing means capable of executing instructions to;

generate at least one channel using a first set of codes;

generate a high-rate channel using a second set of codes;

transmit said at least one channel via a first carrier; and

transmit said high-rate channel via a second carrier that is orthogonal to said first carrier.

2. The apparatus in accordance with claim 1, wherein said at least one channel is a set of channels.

3. The apparatus in accordance with claim 1, wherein said first set of codes is a long Walsh code.

4. The apparatus in accordance with claim 1, wherein said second set of codes is a short Walsh code.

5. The apparatus in accordance with claim 1, wherein said at least one channel is a set of channels, wherein said first set of codes is a long Walsh code, and wherein said second set of codes is a short Walsh code.

6. The apparatus in accordance with claim 2, said digital signal processing means capable of executing further instructions to:

modulate a first instance of said set of channels with an in-phase pseudorandom noise code and an in-phase carrier;

modulate a second instance of said set of channels with a quadrature-phase pseudorandom noise code and a quadrature-phase carrier; and

sum said first instance of said set of channels with said second instance of said set of channels.

7. The apparatus in accordance with claim 2 further said digital signal processing means capable of executing further instructions to:

modulate a first instance of said high-rate channel with an in-phase pseudorandom noise code and an in-phase carrier;

modulate a second instance of said high-rate channel with a quadrature-phase pseudorandom noise code and a quadrature-phase carrier;

invert said second instance of said high-rate channel; and

sum said first instance of said high-rate channel with said second instance of said high-rate channel.

8. The apparatus in accordance with claim 1 further comprising the step of transmitting pilot data on one channel from said set of channels.

9. The apparatus in accordance with claim 3, wherein said second set of codes is a short Walsh code.

10. The apparatus in accordance with claim 9, wherein said at least one channel is a set of channels.

11. The apparatus in accordance with claim 7 further comprising the step of transmitting pilot data on one channel from said set of channels.

12. The apparatus in accordance with claim 2 wherein said set of channels includes a pilot channel, a synchronization channel and a traffic channel.

13. The apparatus in accordance with claim 4 wherein said short code occupies a set of evenly spaced long Walsh codes.

14. The apparatus in accordance with claim 3 wherein said long Walsh codes comprise sixty-four Walsh symbols.

15. A digital signal processing apparatus, comprising:

a memory means for retaining information;

a digital signal processing means communicatively engageable with said memory means, the digital signal processing means capable of executing instructions to;

generate a set of medium rate data channels; and

generate a high rate data channel that is orthogonal to the set of medium rate data channels.

16. The apparatus in accordance with claim 15 wherein said digital signal processing means generates said set of medium rate data channels using a set of long channel code modulators.

17. The apparatus in accordance with claim 16 wherein said digital signal processing means generates said set of high rate data channels using a short channel code modulator.

18. The apparatus in accordance with claim 15 wherein said digital signal processing means generates said set of high rate data channels using a means for transmitting data via a set of evenly distributed long code channels.