Microprocessor development systems
First Claim
1. In a processor including in-circuit emulation means comprising one or more scan chains of serially connected registers for access by an external host computer system, a method of carrying out a debug procedure comprising:
- the host computer system carrying out a debug procedure at a debug processing speed via said scan chains, and selectively interrupting said debug procedure for access to a peripheral or other memory mapped device;
in response to said host computer system selectively interrupting said debug procedure, the host computer system writing via said scan chains into an area of memory of the processor a program for reading and/or writing data at a specified memory location for access to a said peripheral or other memory mapped device; and
the host computer system configuring the processor to execute the program upon the host computer system exiting the debug procedure;
the host computer system exiting the debug procedure causing the processor to execute the program at a full processor speed; and
upon a completion of the execution of the program by the processor, the program causing the host computer system to reenter the debug procedure.
5 Assignments
0 Petitions
Accused Products
Abstract
A procedure and processor are disclosed for avoiding lengthy delays in debug procedures during access by a memory mapped peripheral device. The processor includes in-circuit emulation means comprising one or more scan chains or serially connected registers for access by an external host computer system. The procedure comprises:
a) the host computer system carrying out a debug procedure via said scan chains, and selectively interrupting such debug procedure for access to a peripheral memory mapped device;
b) the host computer system writing into an area or memory of the processor a program for reading and/or writing data at a specified memory location; and
c) the host computer system causing said processor to run said program, and then to return to said debug procedure.
In another aspect, in order to permit small debugging programs to run, in serial scan in circuit emulation processes, on a processor in a deeply embedded application where no program RAM is provided, the processor includes one or more chains of serially connected registers coupled to interface means for access by an external host to enable a serial scan procedure to be carried out, one such chain including a set of serially coupled registers for storing one or more processor instructions read into a set of registers through the interface means, and the processor including address means, for addressing program memory, coupled to said set of registers for addressing the set of registers, and means for reading the processor instructions in the set of registers to an instruction resister of the processor.
75 Citations
12 Claims
-
1. In a processor including in-circuit emulation means comprising one or more scan chains of serially connected registers for access by an external host computer system, a method of carrying out a debug procedure comprising:
-
the host computer system carrying out a debug procedure at a debug processing speed via said scan chains, and selectively interrupting said debug procedure for access to a peripheral or other memory mapped device;
in response to said host computer system selectively interrupting said debug procedure, the host computer system writing via said scan chains into an area of memory of the processor a program for reading and/or writing data at a specified memory location for access to a said peripheral or other memory mapped device; and
the host computer system configuring the processor to execute the program upon the host computer system exiting the debug procedure;
the host computer system exiting the debug procedure causing the processor to execute the program at a full processor speed; and
upon a completion of the execution of the program by the processor, the program causing the host computer system to reenter the debug procedure. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A processor including in-circuit emulation means comprising one or more chains of serially connected registers coupled to interface means for access by an external host to enable a serial scan procedure to be carried out, one such chain including a set of serially coupled registers for storing one or more processor instructions read into a set of registers through the interface means, and the processor including address means, for addressing program memory, coupled to said set of registers for addressing the set of registers, and means for reading the processor instructions in the set of registers to an instruction register of the processor:
-
coupling an input into the registers to an address bus of the processor;
coupling an output of the registers to one input of a multiplexer;
coupling another input of the multiplexer to an output of a program memory of the processor;
providing an output of the multiplexer, wherein the output of the multiplexer is either data received from the program memory or data received from the registers; and
in response to a direction to the processor to address the register set, causing the multiplexer to select its input coupled to the registers, such that data is being read from the registers instead of from the processor'"'"'s program memory. - View Dependent Claims (8, 9, 10, 11)
-
-
12. A method of in-circuit emulation for a processor comprising:
-
providing in the processor one or more chains of serially connected registers coupled to an interface means, one of said one or more chains including a set of serially coupled registers, coupling an input into the registers to an address bus of the processor;
coupling an output of the registers to one input of a multiplexer;
coupling another input of the multiplexer to an output of a program memory of the processor;
providing an output of the multiplexer, wherein the output of the multiplexer is either data received from the program memory or data received from the registers;
(b) feeding to the registers set, through said interface means and said one scan chain, one or more processor instructions, (c) directing the processor to address the register set using its address bus; and
in response to a direction to the processor to address the register set, causing the multiplexer to select its input coupled to the registers, such that data is being read from the registers instead of from the processor'"'"'s program memory.
-
Specification