Dct arithmetic device

• US 6,574,648 B1
• Filed: 10/02/2000
• Issued: 06/03/2003
• Est. Priority Date: 12/14/1998
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nakamura, Tsuyoshi, Oohashi, Masahiro
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US09/601,803
• Time in Patent Office: 974 Days
• Field of Search: 708/402, 708/401, 382/250
• US Class Current: 708/402
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence
• CPC Class Codes: H04N 19/122 Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type
• CPC Class Codes: H04N 19/60 using transform coding

Abstract

There is provided a DCT processor for performing at least one of DCT operation and inverse DCT operation for image data in unit blocks having different sizes. This DCT processor is provided with a bit slice circuit (102) for outputting, bit by bit, the pixel data inputted for each column or row; a first butterfly operation circuit (103) for subjecting the output data of the bit slice circuit (102) to butterfly operation; a ROM address generation circuit (104) for generating continuous ROM addresses; an RAC (105) for reading the data corresponding to the ROM addresses from ROMs (ROM0˜ROM7) and accumulating the data by accumulation circuits (51a˜51h); and a second butterfly operation circuit 106 for subjecting the output data of the RAC 105 to butterfly operation.

Claims

1. A DCT processor performing one-dimensional DCT operation or one-dimensional inverse DCT operation on pixel data of image data in unit blocks each comprising N×

M pixels (N,M;

arbitrary integers from 1 to

     8), comprising;

bit slice means for receiving the pixel data of the image data in each N×

M unit block for each row or column, and slicing, bit by bit, the respective pixel data constituting the input rows or columns, and outputting the sliced pixel data;

control means for outputting a control signal which includes the number of input pixel data that is the number of pixel data constituting each input row or column, and a value indicating that either the DCT operation or the inverse DCT operation is to be performed;

first butterfly operation means for subjecting the output data from the bit slice means to the butterfly operation and outputting the result of the butterfly operation in the case where the control signal outputted from the control means indicates that the number of input pixel data is a power of 2 and that the DCT operation is to be performed, and in the cases other than mentioned above, said first butterfly operation means performing no butterfly operation and outputting the output data of the bit slice means as it is;

address generation means for generating addresses on the basis of bit strings obtained from the output data of the first butterfly operation means, and the number of input pixel data and the value indicating that either the DCT operation or the inverse DCT operation is to be performed, which are included in the control signal;

operation means having eight sets of multiplication result output means and accumulation means, said multiplication result output means outputting the results of multiplication to be used for obtaining the results of the one-dimensional DCT and inverse DCT operations, in accordance with the above-described addresses, and said accumulation means accumulating the output data from the multiplication result output means and outputting the accumulated data; and

second butterfly operation means for subjecting the output data from the operation means to the butterfly operation and outputting the result of the butterfly operation after rearranging it according to the order of input pixel data in the case where the control signal outputted from the control means indicates that the number of input pixel data is a power of 2 and that the inverse DCT operation is to be performed, and in the cases other than mentioned above, said second butterfly operation means performing no butterfly operation and outputting the output data of the operation means after rearranging it according to the order of input pixel data.

2. A DCT processor as described in claim 1 wherein, on the basis of the output data from the first butterfly operation means, and the number of input pixel data, and the value indicating that either the DCT operation or the inverse DCT operation is to be performed, said address generation means generates addresses as follows:

when the control signal indicates that the number of input pixel data is any of 7, 6, 5, and 3, said address generation means generates an address by adding a header address of 2 bits, 3 bits, 4 bits, or 6 bits which indicates the value of the number of input pixel data including the value indicating either the DCT operation or the inverse DCT operation, to a bit string of 7 bits, 6 bits, 5 bits, or 3 bits which is constituted based on the output data from the first butterfly operation means, respectively;

when the control signal indicates that the number of input pixel data is any of 8, 4, and 2 and the DCT operation is to be performed, said address generation means generates an address by adding a header address of 5 bits, 7 bits, or 8 bits which indicates the value of the number of input pixel data including the value indicating that the DCT operation is to be performed, to a bit string of 4 bits, 2 bits, or 1 bit which is constituted based on the result of addition obtained in the butterfly operation by the butterfly operation means, and to a bit string of 4 bits, 2 bits, or 1 bit which is constituted based on the result of subtraction obtained in the butterfly operation, respectively;

when the control signal indicates that the number of input pixel data is any of 8, 4, and 2 and the inverse DCT operation is to be performed, said address generation means generates an address by adding a header address of 5 bits, 7 bits, or 8 bits which indicates the value of the number of input pixel data including the value indicating that the inverse DCT operation is to be performed, to a bit string of 4 bits, 2 bits, or 1 bit which is constituted based on the output of 8 bits, 4 bits, or 2 bits from the first butterfly operation means, respectively; and

said header addresses are bit strings which permit all of the addresses obtained by adding the header addresses to the addresses based on the output data from the first butterfly operation means, to become continuous addresses.

3. A DCT processor as described in claim 1, wherein said multiplication result output means outputs the results of multiplication as follows:

when the control signal outputted from the control means indicates that the number of input pixel data is a power of 2 and the DCT operation is to be performed, said multiplication result output means outputs the result of multiplication with respect to the bit strings obtained from the output data of the first butterfly operation means, according to the DCT matrix operation using fast Fourier transform;

when the control signal outputted from the control means indicates that the number of input pixel data is a value other than a power of 2 and the DCT operation is to be performed, said multiplication result output means outputs the result of multiplication with respect to the bit strings obtained from the output data of the first butterfly operation means, according to the DCT matrix operation;

when the control signal outputted from the control means indicates that the number of input pixel data is a power of 2 and the inverse DCT operation is to be performed, said multiplication result output means outputs the result of multiplication with respect to the bit strings obtained from the output data of the first butterfly operation means, according to the inverse DCT matrix operation using fast Fourier transform; and

when the control signal outputted from the control means indicates that the number of input pixel data is a value other than a power of 2 and the inverse DCT operation is to be performed, said multiplication result output means outputs the result of multiplication with respect to the bit strings obtained from the output data of the first butterfly operation means, according to the inverse DCT matrix operation.

4. A DCT processor as described in claim 1 wherein, when the control signal indicates that the number of input pixel data is a value other than 8, the operation of means which is not used for the operation is halted.

5. A DCT processor as described in claim 1 wherein:

said bit slice means receives 16-bit data as each pixel data to be input, slices this 16-bit data for every two bits, and outputs the sliced data; and

said operation means is provided with, as each of the multiplication result output means, two multiplication result output units placed in parallel with each other, each outputting the result of multiplication, and data obtained by adding the outputs of the two multiplication result output units is accumulated by the corresponding accumulation means.

6. A DCT processor performing one-dimensional DCT operation on pixel data of image data in unit blocks each comprising NXM pixels (N,M:

arbitrary integers not less than

     1), comprising;

bit slice means for receiving the pixel data of the image data in each N×

M unit block for each row or column, and slicing, bit by bit, the respective pixel data constituting the input rows or columns, and outputting the sliced pixel data;

control means for outputting a control signal which indicates the number of input pixel data that is the number of pixel data constituting each input row or column;

butterfly operation means for performing butterfly operation on the output data from the bit slice means and outputting the result of the butterfly operation in the case where the control signal outputted from the control means indicates that the number of input pixel data is a power of 2, and in the cases other than mentioned above, said butterfly operation means performing no butterfly operation and outputting the output data of the bit slice means as it is;

address generation means for generating addresses by using bit strings obtained from the output data of the first butterfly operation means, and the number of input pixel data included in the control signal;

operation means having plural sets of multiplication result output means and accumulation circuits, as many as the maximum value of the number of input pixel data, said multiplication result output means outputting the results of multiplication to be used for obtaining the result of one-dimensional DCT operation, in accordance with the above-described addresses, and said accumulation circuits accumulating the results of multiplication outputted from the respective multiplication result output means and outputting the accumulated results; and

output means for rearranging the output data of the operation means according to the order of input pixel data, and outputting the rearranged data as the result of one-dimensional DCT operation.

7. A DCT processor as described in claim 6 wherein, on the basis of the output data from the first butterfly operation means and the number of input pixel data, said address generation means generates addresses as follows:

when the control signal indicates that the number of input pixel data is a value other than a power of 2, said address generation means generates an address by adding a header address for indicating the number of input pixel data, to an address having the number of bits equal to the number of input pixel data, which is constituted based on the output data from the first butterfly operation means;

when the control signal indicates that the number of input pixel data is a power of 2, said address generation means generates an address by adding a header address for indicating the number of input pixel data, to a bit string having the number of bits equal to half of the number of input pixel data, which is constituted based on the result of the addition obtained in the butterfly operation by the first butterfly operation means, and to a bit string having the number of bits equal to half of the number of input pixel data, which is constituted based on the result of the subtraction obtained in the butterfly operation; and

said header addresses are bit strings which permit all of the addresses obtained by adding the header addresses to the addresses based on the output data from the first butterfly operation means, to become continuous addresses and have the number of bits equal to the maximum value of the number of input pixel data.

8. A DCT processor as described in claim 7, wherein:

the unit block of the image data to be input to the bit slice means is a unit block each comprising N×

M pixels (N,M;

arbitrary integers from 1 to

     8); and

said operation means includes eight sets of multiplication result output means and accumulation means, which is equal to the maximum value of the number of input pixel data.

9. A DCT processor as described in claim 6, wherein said butterfly operation means performs butterfly operation for outputting the values obtained by sequentially adding and subtracting the pixel data, which have been input for each row or column to the bit slice means and sliced bit by bit to be output, starting from the both ends of the input row or column toward the inside.

10. A DCT processor as described in claim 9, wherein:

the unit block of the image data to be input to the bit slice means is a unit block each comprising N×

M pixels (N,M;

arbitrary integers from 1 to

     8); and

said operation means includes eight sets of multiplication result output means and accumulation means, which is equal to the maximum value of the number of input pixel data.

11. A DCT processor as described in claim 6, wherein said multiplication result output means outputs the result of multiplication as follows:

when the control signal outputted from the control means indicates that the number of input pixel data is a power of 2, said multiplication result output means outputs the result of multiplication with respect to the bit strings obtained from the output data of the first butterfly operation means according to the DCT matrix operation using fast Fourier transform; and

when the control signal indicates that the number of input pixel data is a value other than a power of 2, said multiplication result output means outputs the result of multiplication with respect to the bit strings obtained from the output data of the first butterfly operation means according to the DCT matrix operation.

12. A DCT processor as described in claim 11, wherein:

the unit block of the image data to be input to the bit slice means is a unit block each comprising N×

M pixels (N,M;

arbitrary integers from 1 to

     8); and

said operation means includes eight sets of multiplication result output means and accumulation means, which is equal to the maximum value of the number of input pixel data.

13. A DCT processor as described in claim 6 wherein:

the unit block of the image data to be input to the bit slice means is a unit block each comprising N×

M pixels (N,M;

arbitrary integers from 1 to

     8); and

said operation means includes eight sets of multiplication result output means and accumulation means, which is equal to the maximum value of the number of input pixel data.

14. A DCT processor as described in claim 6 wherein, when the control signal indicates that the number of input pixel data is equal to a value other than the maximum value of the number of input pixel data, the operation of means to be unused is halted.

15. A DCT processor as described in claim 6, wherein:

said bit slice means receives 16-bit data as each pixel data to be input, slices this 16-bit data for every two bits, and outputs the sliced data; and

said operation means is provided with, as each of the multiplication result output means, two multiplication result output units placed in parallel with each other, each outputting the result of multiplication, and data obtained by adding the outputs of the two multiplication result output units is accumulated by the corresponding accumulation means.

16. A DCT processor performing one-dimensional inverse DCT operation on pixel data of image data in unit blocks each comprising N×

M pixels (N,M;

arbitrary integers not less than

     1), comprising;

bit slice means for receiving the pixel data of the image data in each N×

M unit block for each row or column, and slicing, bit by bit, the respective pixel data constituting the input rows or columns, and outputting the sliced pixel data;

control means for outputting a control signal which includes the number of input pixel data that is the number of pixel data constituting each input row or column;

address generation means for generating addresses using bit strings obtained from the output data of the bit slice means, and the number of input pixel data included in the control signal;

operation means having plural sets of multiplication result output means and accumulation circuits, as many as the maximum value of the number of input pixel data, said multiplication result output means outputting the results of multiplication to be used for obtaining the result of one-dimensional DCT operation in accordance with the above-described addresses, and said accumulation circuits accumulating the results of multiplication outputted from the respective multiplication result output means and outputting the accumulated results; and

butterfly operation means for performing butterfly operation on the output data from the operation means and outputting the result of the butterfly operation after rearranging it according to the order of input pixel data in the case where the control signal outputted from the control means indicates that the number of input pixel data is a power of 2, and in the cases other than mentioned above, said butterfly operation means performing no butterfly operation and outputting the output data of the operation means after rearranging it according to the order of input pixel data.

17. A DCT processor as described in claim 16 wherein, on the basis of the output data from the bit slice means and the number of input pixel data, said address generation means generates addresses as follows:

when the control signal indicates that the number of input pixel data is a value other than a power of 2, said address generation means generates an address by adding a header address for indicating the number of input pixel data, to an address having the number of bits equal to the number of input pixel data, which is constituted based on the output data of the bit slice means;

when the control signal indicates that the number of input pixel data is a power of 2, said address generation means generates an address by adding a header address for indicating the number of input pixel data, to a bit string having the number of bits equal to half of the number of input pixel data, which is constituted based on the output data from the bit slice means; and

said header addresses are bit strings which permit all of the addresses obtained by adding the header addresses to the addresses based on the output data of the bit slice means to become continuous addresses and have the number of bits equal to the maximum value of the number of input pixel data constituting the input row or column.

18. A DCT processor as described in claim 16, wherein said butterfly operation means performs butterfly operation for outputting the value obtained by addition and the value obtained by subtraction, which addition and subtraction are performed between the value obtained by accumulating the result of multiplication based on the odd-numbered pixel data amongst the pixel data input for each row or column, and the value obtained by accumulating the result of multiplication based on the even-numbered pixel data.

19. A DCT processor as described in claim 16, wherein said multiplication result output means outputs the result of multiplication as follows:

when the control signal outputted from the control means indicates that the number of input pixel data is a power of 2, said multiplication result output means outputs the result of multiplication with respect to the bit strings obtained from the output data of the first butterfly operation means according to the inverse DCT matrix operation using fast Fourier transform; and

when the control signal indicates that the number of input pixel data is a value other than a power of 2, said multiplication result output means outputs the result of multiplication with respect to the bit strings obtained from the output data of the first butterfly operation means according to the inverse DCT matrix operation.

20. A DCT processor as described in claim 16, wherein:

the unit block of the image data to be input to the bit slice means is a unit block each comprising N×

M pixels (N,M;

arbitrary integers from 1 to

     8); and

said operation means includes eight sets of multiplication result output means and accumulation means, which is equal to the maximum value of the number of input pixel data.

21. A DCT processor as described in claim 16, wherein:

said bit slice means receives 16-bit data as each pixel data to be input, slices this 16-bit data for every two bits, and outputs the sliced data; and

said operation means is provided with, as each of the multiplication result output means, two multiplication result output units placed in parallel with each other, each outputting the result of multiplication, and data obtained by adding the outputs of the two multiplication result output units is accumulated by the corresponding accumulation means.

22. A DCT processor as described in claim 16,

wherein, when the control signal indicates that the number of input pixel data is equal to a value other than the maximum value of the number of input pixel data, the operation of means to be unused is halted.