Software prefetch system and method for predetermining amount of streamed data

• US 6,574,712 B1
• Filed: 04/14/2000
• Issued: 06/03/2003
• Est. Priority Date: 11/08/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Silha, Edward John, Ray, David Scott, Kahle, James Allan, Mayfield, Michael John, Tendler, Joel M., OʼConnell, Francis Patrick
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US09/550,180
• Time in Patent Office: 1,145 Days
• Field of Search: 711/137, 711/122, 711/119, 711/213, 712/207, 712/237, 712/239
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction is used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine. The instruction also limits the amount of data to be prefetched.

Claims

1. A data processing system comprising:

a processor having a load/store unit including a level one (L1) cache;

a prefetch engine coupled to the load/store unit;

a level two (L2) cache coupled to the L1 cache and the prefetch engine;

a level three (L3) cache coupled to the L2 cache and to the prefetch engine; and

circuitry operable for overriding the prefetch engine in response to a single instruction executed in the processor, wherein the overriding circuitry causes the prefetch engine to prefetch a predetermined stream of cache lines concurrently into the L1, L2, and L3 caches.

2. The system as recited in claim 1, wherein the prefetch engine, in response to the overriding circuitry, prefetches a cache line into the L1 cache, one or more cache lines into the L2 cache, and one or more cache lines into the L3 cache.

3. The system as recited in claim 2, wherein the prefetch engine, in response to the overriding circuitry, prefetches cache line n+1 into the L1 cache, cache lines n+2, n+3, n+4, and n+5 into the L2 cache, and a block of cache lines into the L3 cache.

4. The system as recited in claim 3, wherein the prefetch engine, in response to the overriding circuitry, prefetches a plurality of blocks of cache lines into the L3 cache, wherein a block comprises a plurality of cache lines.

5. The system as recited in claim 3, wherein the prefetch engine prefetches another block of cache lines into the L3 cache after the processor has issued demands for cache lines n+1, n+2, n+3, and n+4.

6. The system as recited in claim 1, wherein the prefetch engine stops prefetching of the stream of cache lines in response to a predetermined variable in the instruction.

7. A multiprocessor system comprising:

a first processor including a first level one (L1) cache and a first prefetch engine;

a second processor including a second L1 cache and a second prefetch engine;

a level two (L2) cache shared by the first and second processors;

a fabric coupled to the L2 cache and adaptable for coupling to a third processor;

a level three (L3) cache;

system memory coupled to the L3 cache;

a first bus system for transferring data between the first L1 cache, L2 cache, and L3 cache and load misses from the first L1 cache to the first prefetch engine;

a second bus system for transferring data between the second L1 cache, L2 cache, and L3 cache and load misses from the second L1 cache to the second prefetch engine;

first circuitry operable for overriding the first prefetch engine in response to a first single instruction executed in the first processor, wherein the first overriding circuitry causes the first prefetch engine to prefetch a predetermined first stream of cache lines concurrently into the first L1, L2, and L3 caches.

8. The system as recited in claim 7, wherein the first prefetch engine further comprises:

circuitry for sending a prefetch request from the prefetch engine to the L2 cache over the private prefetch request bus; and

circuitry for prefetching cache line n+1 into the L1 cache in response to the prefetch request over the bus system.

9. The system as recited in claim 8, wherein the first prefetch engine further comprises:

circuitry for prefetching cache line n+2 into the L2 cache in response to the prefetch request.

10. The system as recited in claim 8, wherein the first prefetch engine further comprises:

circuitry for prefetching a block of N cache lines into the L3 cache in response to the prefetch request and the signal, where N is greater than 1.

11. In a data processing system comprising a processor having a load/store unit including a level one (L1) cache, a prefetch engine coupled to the load/store unit, a level two (L2) cache coupled to the L1 cache and the prefetch engine, and a level three (L3) cache coupled to the L2 cache and to the prefetch engine, a method comprising the steps of:

overriding the prefetch engine in response to a single instruction executed in the processor; and

in response to the overriding step, causing the prefetch engine to prefetch a predetermined stream of cache lines concurrently into the L1, L2, and L3 caches.

12. The method as recited in claim 11, wherein the causing step further comprises the step of prefetching a cache line into the L1 cache, one or more cache lines into the L2 cache, and one or more cache lines into the L3 cache.

13. The method as recited in claim 12, wherein the causing step further comprises the step of prefetching a cache line n+1 into the L1 cache, cache lines n+2, n+3, n+4, and n+5 into the L2 cache, and a block of cache lines into the L3 cache.

14. The method as recited in claim 11, further comprising the step of the prefetch engine stopping the prefetching of the stream of cache lines in response to a predetermined variable in the instruction.

15. In a multiprocessor system comprising a first processor including a first level one (L1) cache and a first prefetch engine, a second processor including a second L1 cache and a second prefetch engine, a level two (L2) cache shared by the first and second processors, a fabric coupled to the L2 cache and adaptable for coupling to a third processor, a level three (L3) cache, system memory coupled to the L3 cache, a first bus system for transferring data between the first L1 cache, L2 cache, and L3 cache and load misses from the first L1 cache to the first prefetch engine, and a second bus system for transferring data between the second L1 cache, L2 cache, and L3 cache and load misses from the second L1 cache to the second prefetch engine, a method comprising the steps of:

overriding the first prefetch engine in response to a first single instruction executed in the first processor; and

in response to the overriding step, causing the first prefetch engine to prefetch a predetermined first stream of cache lines concurrently into the first L1, L2, and L3 caches.

16. The method as recited in claim 15, further comprising the steps of:

sending a prefetch request from the prefetch engine to the L2 cache over the private prefetch request bus; and

prefetching cache line n+1 into the L1 cache in response to the prefetch request over the bus system.