Dynamic power saving by monitoring CPU utilization

• US 6,574,739 B1
• Filed: 04/14/2000
• Issued: 06/03/2003
• Est. Priority Date: 04/14/2000
• Status: Expired due to Term

• Current Assignee: Compal Electronics Incorporated
• Original Assignee: Compal Electronics Incorporated
• Inventors: Liu, Chun-Chih, Kung, Shao-Tsu, Chen, Yi-Chang, Cheng, Chih-Chuan
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US09/550,321
• Time in Patent Office: 1,145 Days
• Field of Search: 713/300, 713/320, 713/322-340, 713/501
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A CPU activity monitoring circuit is electrically connected to a CPU. This circuit monitors the state of a bus signal line on the CPU, as there is a strong correlation between the state of this line and the processing load of the CPU. This circuit can interrupt the processor to force an interrupt service call to a BIOS routine. This BIOS routine will adjust the internal clock frequency, or internal operating voltage, of the CPU based upon the perceived processing load of the CPU.

Claims

1. A computer system comprising:

a central processing unit (CPU) for processing data or executing programs using a predetermined internal clock frequency, the CPU being able to accept a predetermined range of input voltages and the CPU being able to change its internal clock frequency;

a power regulator electrically connected to the CPU, the power regulator selectably providing a required input voltage to the CPU;

memory electrically connected to the CPU for storing data and programs, the memory comprising a CPU activity adjusting program being executed in the CPU;

a CPU activity monitoring circuit electrically connected to the CPU for monitoring processing loads of the CPU, the CPU activity monitoring circuit comprising a CPU activity register for storing a load parameter that corresponds to a perceived processing load of the CPU;

wherein the adjusting program adjusts the power regulator to change the input voltage of the CPU, or to change the internal clock frequency of the CPU, according to the load parameter stored in the CPU activity register.

2. The computer system of claim 1 wherein the CPU comprises a M/IO signal line, a strobed frequency of the M/IO signal line representing a correspondingly perceived load of the CPU, and the CPU activity monitoring circuit is electrically connected to the M/IO signal line, the CPU activity monitoring circuit using the M/IO signal line to determine the perceived processing load of the CPU.

3. The computer system of claim 2 wherein the CPU activity monitoring circuit accumulates over a predetermined period of time the strobed frequency of the M/IO signal line and stores accumulated results as the load parameter in the CPU activity register.

4. The computer system of claim 3 wherein the CPU activity monitoring circuit comprises a series resistor-capacitor circuit (RC circuit) electrically connected to the M/IO signal line and an analog-to digital (A/D) converter electrically connected to the RC circuit;

wherein the RC circuit develops an analog voltage according to the strobed frequency of the M/IO signal line and then the analog voltage is converted into the load parameter stored in the CPU activity register.

5. The computer system of claim 1 wherein the memory comprises a Basic Input Output System (BIOS) program, and the CPU activity adjusting program is part of the BIOS program.

6. The computer system of claim 1 wherein the CPU activity monitoring circuit interrupts the CPU when the perceived load of the CPU crosses at least a predetermined threshold value, and the CPU executes the CPU activity adjusting program when it services the interrupt.

7. The computer system of claim 1 further comprising a clock with a predetermined frequency electrically connected to the CPU, and the CPU comprising a clock multiplier register with a multiplier value stored therein, the internal clock frequency of the CPU being determined by the product of the frequency of the clock and the multiplier value stored in the clock multiplier register.

8. The computer system of claim 7 wherein the CPU activity adjusting program changes the internal clock frequency of the CPU by changing the multiplier value stored in the clock multiplier register.

9. The computer system of claim 1 wherein the required input voltage to the CPU from the power regulator is selectable from a plurality of predetermined voltages.

10. The computer system of claim 9 wherein the plurality of predetermined voltages lie within the predetermined range of input voltages accepted by the CPU.

11. The computer system of claim 1 wherein the CPU comprises a voltage identification register (VID register) with a VID value stored therein, the VID) register being electrically connected to the power regulator, and the power regulator provides the required input voltage to the CPU according to the VID value sent from VID register.

12. The computer system of claim 11 wherein the CPU activity adjusting program adjusts the power regulator to change the input voltage of the CPU by changing the VID value stored in the VID register.