Hierarchical layout method for integrated circuits

• US 6,574,779 B2
• Filed: 04/12/2001
• Issued: 06/03/2003
• Est. Priority Date: 04/12/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lovejoy, Steve G., Allen, Robert J., Cohn, John M.
• Primary Examiner(s): Wong, Don
• Assistant Examiner(s): CHEN, SHIH CHAO
• Application Number:
  US09/833,479
• Publication Number:
  US 20020194575A1
• Time in Patent Office: 782 Days
• Field of Search: 716/1, 716/4, 716/5, 716/7, 716/12, 716/17
• US Class Current: 716/103
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method for hierarchical layout of an electronic design using an electronic computer aided design system, wherein the method includes generating a parameterized pattern library and using an existing netlist and analyze in a pattern recognizer, from which a list of associations between the pattern library and the netlist is created. Renesting then occurs wherein the netlist using the list of associations is used for generating a hierarchical layout of the electronic components in the design.

Claims

1. A method for creating a parameterized pattern library for a hierarchical layout of an electronic design, said method comprising:

selecting at least one layout generator;

creating rules for generating a layout netlist for a specific instance of each layout generator, said rules comprising a topology and node parameters of said layout netlist, said node parameters being calculated as mathematical expressions of netlist parameters of said layout netlist; and

calculating matching criteria and parameter derivation rules from said rules.

2. The method of claim 1, wherein said rules comprise flattening rules for generating a transistor level netlist, wherein said transistor level netlist comprises wiring connections and location of nodes of said transistor level netlist.

3. The method of claim 1, wherein said matching criteria includes required “

p/n”

type transistor ratios, equality between different said parameters, and a minimum and maximum bounds on said parameters.

4. The method of claim 1, wherein said parameter derivation rules comprise an inversion parameter of said matching criteria.

5. A computer implemented design method for hierarchical layout of an electronic design, the method comprising:

generating a parameterized pattern library;

inputting a netlist into a pattern recognizer;

creating a list of associations between said pattern library and said netlist using said pattern recognizer; and

renesting said netlist using said list of associations.

6. The method of claim 5, further comprising generating a hierarchical layout of said electronic design.

7. The method of claim 5, wherein said generating of said parameterized pattern library includes loading parameters used by said pattern recognizer, said parameters include:

a) for each pattern, identifying and matching said netlist;

b) a set of constraint equations over properties of matched elements; and

c) a set of expressions for deriving parameters on said matched elements to be inserted in place of a matched pattern.

8. The method of claim 5, wherein said generating of said parameterized pattern library includes deriving elements for a schematic-driven layout generation, said elements include parameters comprising:

a) an element netlist for each said element, said element netlist includes named sub-elements having properties and topology of electrical connections; and

b) each said property on each said sub-element is defined as a mathematical function for each of said derived elements.

9. The method of claim 8, wherein said property of said sub-element is derived starting from a set of equations with one formal parameter wherein said derivation includes:

selecting an equation with one formal parameter;

removing from said set of equations and solve for said one formal parameter by equation inversion;

adding to a derived parameter list;

reducing said set of equations; and

determining whether unselected equations with no formal parameters remain, and removing said unselected equations with no-formal parameters from a solution set of equations and add to a list of constraint equations if there are remaining said unselected equations, and if not, then determining whether there are any equations remaining from said set of equations with one formal parameter.

10. The method of claim 9, wherein said selecting of an equation with one formal parameter further includes:

determining whether said equation with one formal parameter exist,

if no said equation with one formal parameter exist, the method further comprises;

a) selecting an equation with minimum number of formal parameters;

b) selecting a formal parameter in said equation in a);

c) solving for said parameter in a) by inverting functions; and

d) reducing said set of equations by substituting said solution.

11. A computer implemented design method for hierarchical layout of an electronic design, the method comprising:

generating a parameterized pattern library;

inputting a netlist into a pattern recognizer;

creating a list of associations between said pattern library and said netlist using said pattern recognizer; and

renesting said netlist using said list of associations,

wherein said creating of said parameterized pattern library comprises selecting and loading a list of layout generators, wherein each layout generator comprises;

creating rules of a schematic pattern for generating a generator layout netlist for a specific instance of said layout generator, said schematic pattern comprising a netlist topology and parameters for nodes of said generator layout netlist calculated as mathematical expressions of said parameters of said generator layout;

calculating a matching criteria from said pattern schematic, and parameter derivation rules, wherein said pattern recognizer for said layout generator is created for a required topology with said matching criteria.

12. The method of claim 11, wherein said step of renesting includes:

creating renesting subgraphs that match said required topology and accepted by said matching criteria; and

substituting each said renesting subgraph with a node represented by each said layout generator, with parameters calculated using said parameter derivation rules.

13. A system for designing a hierarchical layout of an electronic design forming part of an electronic computer, said system comprising:

a parameterized pattern library generator;

a pattern recognizer operably connected to said parameterized pattern library generator; and

a renester, whereby said parameterized pattern library generator creates parameters used to form a list of associations between a netlist and said patent recognizer.

14. The system of claim 13, further comprising a generator of a hierarchical layout of said electronic design, said generator is operably connected to said renester.

15. The system of claim 13, wherein said parameterized pattern library includes a memory for storing parameters used by said pattern recognizer, said parameters include:

a) for each pattern, identifying and matching said netlist;

b) a set of constraint equations over properties of said matched elements; and

c) a set of expressions for deriving parameters on said matched elements to be inserted in place afraid matched pattern.

16. A system for designing a hierarchical layout of an electronic design forming part of an electronic computer, said system comprising:

a parameterized pattern library;

a pattern recognizer operably connected to said parameterized pattern library; and

a renester, whereby said parameterized pattern library creates parameters used to form a list of associations between a netlist and said pattern recognizer,

wherein said parameterized pattern library and said pattern recognizer comprise a portion of said electronic computer for enabling a method for selecting and loading a list of layout generators, wherein each said layout generator executes instructions that include;

creating rules of a schematic pattern for generating a generator layout netlist for a specific instance of said layout generator, said schematic pattern comprising a netlist topology and parameters for nodes of said generator layout netlist calculated as mathematical expressions of said parameters of said generator layout;

calculating a matching criteria from said pattern schematic, and parameter derivation rules, wherein said pattern recognizer for said layout generator is created for a required topology with said matching criteria.

17. The system of claim 16, wherein said renester comprises a portion of said central processing unit for creating renesting subgraphs that match said required topology and accepted by said matching criteria;

and substituting each said renesting subgraph with a node represented by each said layout generator, with parameters calculated using said parameter derivation rules.

18. A system for designing a hierarchical layout of an electronic design forming part of an electronic computer, said system comprising:

a parameterized pattern library;

a pattern recognizer operably connected to said parameterized pattern library; and

a renester, whereby said parameterized pattern library creates parameters used to form a list of associations between a netlist and said pattern recognizer,

wherein said pattern library includes elements derived for a schematic-driven layout generator, said elements include parameters comprising;

a) an element netlist for each said element, said element netlist includes named sub-elements having properties and topology of electrical connections; and

b) each said property on each said sub-element is defined as a mathematical function for each of said derived elements.

19. The system of claim 18, wherein said property of said sub-element is derived starting from a set of equations with one formal parameter, wherein said derivational method includes:

selecting an equation with one formal parameter;

removing from said set of equations and solve for said one formal parameter by equation inversion;

adding to a derived parameter list;

reducing said set of equations; and

determining whether unselected equations with no formal parameters remain, and removing said unselected equations with no-formal parameters from a solution set of equations and add to a list of constraint equations if there are remaining said unselected equations, and if not, then determining whether there are any equations remaining from said set of equations with one formal parameter.

20. The system of claim 19, wherein said derivational method as to selecting an equation with one formal parameter further includes:

determining whether said equation with one formal parameter exist,

if no said equation with one formal parameter exist, the method further comprises;

a) selecting an equation with minimum number of formal parameters;

b) selecting a formal parameter in said equation in a);

c) solving for said parameter in a) by inverting functions; and

d) reducing said set of equations by substituting said solution.

21. A program storage device readable by a computer system, tangibly embodying a program of instructions executable by said system to perform a method for design of a hierarchical layout of an electronic design forming part of an electronic computer aided design system, said method comprising:

generating a parameterized pattern library;

inputting said parameterized pattern library and a netlist into a pattern recognizer;

creating a list of associations between said pattern library and said netlist using said pattern recognizer; and

renesting said netlist using said list of associations.

22. The program storage device of claim 21, further comprising generating a hierarchical layout of said electronic design.

23. The program storage device of claim 21, wherein said inputting of said pattern library includes loading parameters used by said pattern recognizer, said parameters include:

a) for each pattern, identifying and matching said netlist;

b) a set of constraint equations over properties of said matched elements; and

c) a set of expressions for deriving parameters on said matched elements to be inserted in place of said matched pattern.

24. A program storage device readable by a computer system, tangibly embodying a program of instructions executable by said system to perform a method for design of a hierarchical layout of an electronic design forming part of an electronic computer aided design system, said method comprising:

inputting a parameterized pattern library and a netlist into a pattern recognizer;

creating a list of associations between said pattern library and said netlist using said pattern recognizer; and

renesting said netlist using said list of associations,

wherein said inputting of said parameterized pattern library and said pattern recognizer comprises selecting and loading a list of layout generators, wherein each said layout generator comprises;

creating rules of a pattern schematic for generating a generator layout netlist for a specific instance of said layout generator, said schematic pattern comprising a netlist topology and parameters for nodes of said generator layout netlist calculated as mathematical expressions of said parameters of said generator layout;

calculating a matching criteria from said pattern schematic, and parameter derivation rules, wherein said pattern recognizer for said layout generator is created for a required topology with said matching criteria.

25. The program storage device of claim 24, wherein said step of renesting includes:

creating renesting subgraphs that match said required topology and accepted by said matching criteria; and

substituting each said renesting subgraph with a node represented by each said layout generator, with parameters calculated using said parameter derivation rules.

26. A program storage device readable by a computer system, tangibly embodying a program of instructions executable by said system to perform a method for design of a hierarchical layout of an electronic design forming part of an electronic computer aided design system, said method comprising:

inputting a parameterized pattern library and a netlist into a pattern recognizer;

creating a list of associations between said pattern library and said netlist using said pattern recognizer; and

renesting said netlist using said list of associations,

wherein said inputting of said pattern library includes deriving elements for a schematic-driven layout generation, said elements include parameters comprising;

a) an element netlist for each said element, said element netlist includes named sub-elements having properties and topology of electrical connections; and

b) each said property on each said sub-element is defined as a mathematical function for each of said derived elements.

27. The program storage device of claim 26, wherein said property of said sub-element is derived starting from a set of equations with one formal parameter wherein said derivation includes:

selecting an equation with one formal parameter;

removing from said set of equations and solve for said one formal parameter by equation inversion;

adding to a derived parameter list;

reducing said set of equations; and

determining whether unselected equations with no formal parameters remain, and removing said unselected equations with no-formal parameters from a solution set of equations and add to a list of constraint equations if there are remaining said unselected equations, and if not, then determining whether there are any equations remaining from said set of equations with one formal parameter.

28. The program storage device of claim 27, wherein said selecting of an equation with one formal parameter further includes:

determining whether said equation with one formal parameter exist,

if no said equation with one formal parameter exist, the method further comprises;

a) selecting an equation with minimum number of formal parameters;

b) selecting a formal parameter in said equation in a);

c) solving for said parameter in a) by inverting functions; and

d) reducing said set of equations by substituting said solution.