Security card and a computer system provided with an interface for reading a security card

• US 6,575,373 B1
• Filed: 09/15/2000
• Issued: 06/10/2003
• Est. Priority Date: 09/17/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakano, Hiroo
• Primary Examiner(s): Lee, Michael G.
• Assistant Examiner(s): PAIK, STEVEN SANGYUL
• Application Number:
  US09/662,864
• Time in Patent Office: 998 Days
• Field of Search: 235/380, 235/487, 235/492, 235/382, 380/25
• US Class Current: 235/492
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 2207/7219 Countermeasures against side channel or fault attacks
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 19/07363 by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis

Abstract

A security card 20 including a CPU 1 for executing instruction sequences such as a password verifying routine, a memory 2 configured to store secret data such as the password and so forth, a random signal generation circuit 4 configured to generate a wait signal which is output in order to halt the operation of the CPU 1. When the wait signal is input, the CPU 1 halts its operation for a short time such as one to several clocks. In accordance with the security card 20, the operation of the CPU 1 can be deferred for a short time in an arbitrary timing in order to make it difficult to analyze the operation of the CPU 1.

Claims

1. A security card provided with an IC chip comprising:

a memory element configured to store secret data;

a reading circuit configured to read said secret data as stored in said memory element;

a connection terminal configured to receive an external signal;

a connection configured to transmit an output signal; and

a random signal generation circuit configured to transmit a wait signal to said reading circuit in response to said external signal in a non-periodic manner, wherein

said reading circuit halts its reading operation in response to said wait signal in a non-periodic manner with the operation state being maintained in such a state as having been taken just before the reading circuit halts and, after resuming, the halted operation is continued from said operation state as maintained.

2. The security card as claimed in claim 1, wherein a length of time of the wait signal is a same length or shorter than a time for the reading circuit to read the secret data.

3. The security card as claimed in claim 1, wherein,

said reading circuit is configured to receive a password from an external source, to match the password against secret data stored in a memory in order to verify whether or not the password is in agreement with the secret data, and to output a result of said verifying under the control of the wait signal.

4. A security card provided with an IC chip comprising:

a memory element configured to store secret data;

a reading circuit configured to read said secret data as stored in said memory element;

a connection terminal configured to receive an external an clock signal;

a connection terminal configured to transmit an output signal; and

a clock signal control circuit configured to intercept said external clock signal to be supplied to said reading circuit and to transfer the external clock signal as an operating clock signal to said reading circuit in a non-periodic manner,

wherein said reading circuit halts its reading operation while the supply of said operating clock signal is deferred with the operation state being maintained in such a state as having been taken just before the reading circuit halts and, after resuming, the halted operation is continued from said operation state as maintained.

5. The security card as claimed in claim 4, wherein a length of time of the wait signal is a same length or shorter than a time for the reading circuit to read the secret data.

6. The security card as claimed in claim 4, wherein,

said reading circuit is configured to receive a password from an external source, to match the password against secret data stored in a memory in order to verify whether or not the password is in agreement with the secret data, and to output a result of said verifying under the control of the operating clock signal.

7. A security card provided with an IC chip comprising:

a memory element configured to store secret data;

a reading circuit configured to read said secret data as stored in said memory element;

a connection terminal configured to receive an external signal;

a connection terminal configured to transmit an output signal;

a clock signal control circuit configured to intercept said external clock signal to be supplied to said reading circuit and tp transfer the external clock signal as an operating clock signal to said reading circuit in a non-periodic manner; and

a random signal generation circuit configured to transmit a wait signal in a non-periodic manner;

wherein,

said clock signal control circuit is configured to defer said operating clock signal in a non-periodic manner in response to said wait signal input from said random signal generation circuit, and

said reading circuit halts its reading operation while the supply of said operating clock signal is deferred with the operation state being maintained in such a state as having been taken just before the reading circuit halts and, after resuming, the halted operation is continued from said operation state as maintained.

8. The security card as claimed in claim 7, wherein a length of time of the wait signal is a same length or shorter than a time for the reading circuit to read the secret data.

9. The security card as claimed in claim 8, wherein,

said reading circuit is configured to receive a password from an external source, to match the password against secret data stored in a memory in order to verify whether or not the password is in agreement with the secret data, and to output a result of said verifying under the control of the operating clock signal.

10. A computer system provided with an interface configured to read a security card, said security card comprising

a memory element configured to store a start up password for booting said computer system;

a reading circuit configured to read said start up password as stored in said memory element;

a connection terminal configured to receive an external signal;

a connection terminal configured to transmit an output signal; and

a random signal generation circuit configured to transmit a wait signal to said reading circuit in response to said external signal in a non-periodic manner, wherein

said reading circuit halts its reading operation in response to said wait signal in a non-periodic manner with the operation state being maintained in such a state as having been taken just before the reading circuit halts and, after resuming, the halted operation is continued from said operation state as maintained, and wherein

if the start up password is valid, said computer system starts its operation.

11. The security card as claimed in claim 10, wherein a length of time of the wait signal is a same length or shorter than a time for the reading circuit to read the secret data.

12. The computer system as claimed in claim 10, wherein,

said reading circuit is configured to receive a password from said computer system and matches the password against secret data stored in said memory in order to verify whether or not the password is in agreement with the secret data under the control of the wait signal, and

if the start up password is valid, said computer system starts its operation.

13. A computer system provided with an interface configured to read a security card, said security card comprising:

a memory element configured to store a start up password for booting said computer system;

a reading circuit configured to read said start up password as stored in said memory element;

a connection terminal configured to receive an external clock signal;

a connection terminal configured to transmit an output signal; and

a clock signal control circuit configured to serve to intercept said external clock signal to be supplied to said reading circuit and to transfer the external clock signal as an operating clock signal to said reading circuit in a non-periodic manner, wherein,

said reading circuit halts its reading operation while the supply of said operating clock signal is deferred with the operation state being maintained in such a state as having been taken just before the reading circuit halts and, after resuming, the halted operation is continued from said operation state as maintained, and

if the start up password is valid, said computer system starts its operation.

14. The security card as claimed in claim 13, wherein a length of time of the wait signal is a same length or shorter than a time for the reading circuit to read the secret data.

15. The computer system as claimed in claim 13 wherein

and to said reading circuit is configured to receive a password from said computer system and to match the password against secret data stored in said memory in order to verify whether or not the password is in agreement with the secret data under the control of said operating clock signal, and

if the start up password is valid, said computer system starts its operation.

16. A computer system provided with an interface for reading a security card, said security card comprising:

a memory element configured to store a start up password for booting said computer system;

a reading circuit configured to read said start up password as stored in said memory element;

a connection terminal configured to receive an external signal;

a connection terminal configured to transmit an output signal;

a clock signal control circuit configured to intercept said external clock signal to be supplied to said reading circuit and to transfer the external clock signal as an operating clock signal to said reading circuit in a non-periodic manner; and

a random signal generation circuit configured to transmit a wait signal in a non-periodic manner;

wherein,

said clock signal control circuit is configured to defer said operating clock signal in a non-periodic manner in response to said wait signal input from said random signal generation circuit,

said reading circuit halts its reading operation while the supply of said operating clock signal is deferred with the operation state being maintained in such a state as having been taken just before the reading circuit halts and, after resuming, the halted operation is continued from said operation state as maintained, and

if the start up password is valid, said computer system starts its operation.

17. The security card as claimed in claim 16, wherein a length of time of the wait signal is a same length or shorter than a time for the reading circuit to read the secret data.

18. The computer system as claimed in claim 16 wherein,

said reading circuit is configured to receive a password from said computer system and to match the password against secret data stored in said memory in order to verify whether or not the password is in agreement with the secret data under the control of said operating clock signal, and

if the start up password is valid, said computer system starts its operation.