Inspectable buried test structures and methods for inspecting the same

• US 6,576,923 B2
• Filed: 06/21/2002
• Issued: 06/10/2003
• Est. Priority Date: 04/18/2000
• Status: Expired due to Term

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Pinto, Gustavo A., Mantalas, Lynda C., Long, Robert Thomas, Satya, Akella V. S., Richardson, Neil
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Huynh, Andy
• Application Number:
  US10/178,329
• Publication Number:
  US 20020187582A1
• Time in Patent Office: 354 Days
• Field of Search: 257/48, 438/11, 438/14, 438/15, 438/18
• US Class Current: 257/48
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 977/712 formed from plural layers of nanosized material, e.g. stacked structures
• CPC Class Codes: Y10S 977/723 On an electrically insulating substrate
• CPC Class Codes: Y10S 977/888 Shaping or removal of materials, e.g. etching
• CPC Class Codes: Y10S 977/89 Deposition of materials, e.g. coating, cvd, or ald

Abstract

Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.

Claims

1. A semiconductor die comprising:

a substrate;

a lower test structure formed in a lower conductive layer of the semiconductor die, the lower test structure having a first end and a second end, wherein the first end is designed to be coupled to the substrate, the lower conductive layer being formed over the substrate;

an insulating layer formed over the lower conductive layer;

a first upper test structure formed in an upper conductive layer of the semiconductor die, the upper test structure being designed to be coupled with the second end of the lower test structure, the upper conductive layer being formed over the insulating layer; and

a second upper test structure formed in the upper conductive layer, the second upper test structure being designed to be floating with respect to the first upper test structure, wherein an end of the second upper test structure is near the first upper test structure so that the first and second upper test structures fit within a single swath of a charged beam.

2. The semiconductor die of claim 1 wherein an open electrical defect is detectable within the first test structure by performing a voltage contrast inspection of the upper test structure.

3. The semiconductor die of claim 2 further comprising:

a first via coupled between the first end of the lower test structure and the substrate.

4. The semiconductor die of claim 1 wherein the lower test structure is an extended conductive line.

5. The semiconductor die of claim 1 wherein the upper test structure is a voltage contrast element.

6. A semiconductor die comprising:

a substrate;

a lower test structure formed in a lower conductive layer of the semiconductor die, the lower test structure having a first end and a second end, wherein the first end is coupled to the substrate, the lower conductive layer being formed over the substrate;

an insulating layer formed over the lower conductive layer;

a first upper test structure formed in an upper conductive layer of the semiconductor die, the upper test structure being coupled with the second end of the lower test structure, the upper conductive layer being formed over the insulating layer, wherein the upper test structure is coupled with the lower second end of the lower test structure through a plurality of vias within a plurality of insulating layers that are positioned between the lower and upper conductive layers and through a plurality of intervening test structures formed in a plurality of intervening conductive layers positioned between the upper and lower conductive layers; and

a second upper test structure formed in the upper conductive layer, the second upper test structure being designed to be floating with respect to the first upper test structure, wherein an end of the second upper test structure is near the first upper test structure so that the first and second upper test structures fit within a single swath of a charged beam.

7. The semiconductor die of claim 6 wherein the second upper test structure is also coupled to a second lower test structure formed within one of the intervening conductive layers, the second lower test structure being electrically floating.

8. The semiconductor die of claim 7 wherein the second upper test structure is coupled with the second lower test structure through a plurality of vias spaced over the length of the second lower test structure.

9. A semiconductor test structure for facilitating detection of defects, comprising:

a substrate;

a first coupled test structure formed within a first conductive layer formed over and designed to be coupled with the substrate;

a second coupled test structure formed within a second conductive layer formed over and designed to be coupled with the first coupled test structure;

a second floating test structure formed within the second conductive layer which is designed not to be coupled with the first coupled test structure; and

a third coupled test structure formed within a third conductive layer formed over and designed to be coupled with the second coupled test structure.

10. The semiconductor test structure as recited in claim 9, further comprising:

a first nonconductive layer formed between the first conductive layer and the substrate;

a first conductive plug formed within the first nonconductive layer and positioned to couple the first coupled test element with the substrate;

a second nonconductive layer formed between the first conductive layer and the second conductive layer;

a second conductive plug formed within the second nonconductive layer and positioned to couple the first coupled test element with the second coupled test element;

a third nonconductive layer formed between the second conductive layer and the third conductive layer; and

a third conductive plug formed within the third nonconductive layer and positioned to couple the second coupled test element with the third coupled test element.

11. The semiconductor test structure as recited in claim 9, further comprising a third floating test structure formed within the third conductive layer which is designed not to be coupled with the second coupled test structure.

12. The semiconductor test structure as recited in claim 11, further comprising:

a first nonconductive layer formed between the first conductive layer and the substrate;

a first conductive plug formed within the first nonconductive layer and positioned to couple the first coupled test element with the substrate;

a second nonconductive layer formed between the first conductive layer and the second conductive layer;

a second conductive plug formed within the second nonconductive layer and positioned to couple the first coupled test element with the second coupled test element;

a third nonconductive layer formed between the second conductive layer and the third conductive layer; and

a third conductive plug formed within the third nonconductive layer and positioned to couple the second coupled test element with the third coupled test element.

13. The semiconductor test structure as recited in claim 12, further comprising a plurality of third conductive plugs, wherein at least one of the third conductive plugs is positioned to couple the second coupled test element with the third coupled test element and the remaining third conductive plugs are positioned to couple the second floating test element with the third floating test element.