Semiconductor processing methods, methods of forming electronic components, and transistors

• US 6,576,939 B1
• Filed: 01/10/2000
• Issued: 06/10/2003
• Est. Priority Date: 07/30/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Korn, David, Gilton, Terry
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/480,072
• Time in Patent Office: 1,247 Days
• Field of Search: 257/286, 257/288, 257/297, 257/327, 438/586, 438/233, 438/299, 438/597
• US Class Current: 257/288
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/32105 Oxidation of silicon-containing layers
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers respectively have an exposed outer edge spaced inside of the substrate periphery. Etching is conducted into the higher oxidation rate material at a faster rate than any etching which occurs into the lower oxidation rate material. Then, the substrate is exposed to the oxidizing atmosphere. In another implementation, a stack of at least two conductive layers for an electronic component is formed. The two conductive layers have different oxidation rates when exposed to an oxidizing atmosphere. The layer with the higher oxidation rate has an outer lateral edge which is recessed inwardly of a corresponding outer lateral edge of the layer with the lower oxidation rate. The stack is exposed to the oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second layers. In yet another implementation, a transistor comprises a semiconductive substrate and a gate stack formed thereover. The stack in at least one cross section defines a channel length within the substrate of less than 1 micron, with the stack comprising conductive material formed over a gate dielectric layer. An insulative layer is formed on outer lateral edges of the conductive material, with such layer having opposing substantially continuous straight linear outer lateral edges over all conductive material of the gate stack within the one cross section.

Claims

1. A transistor comprising:

a semiconductive substrate;

a stack of a gate dielectric layer over the semiconductive substrate, a first conductive layer over the gate dielectric layer, a second conductive layer different in composition from the first and received over the first, and an insulative cap over the second conductive layer;

the first conductive layer of the stack having opposing outer lateral edges which are spaced less than one micron apart defining a channel length within the semiconductive substrate of less than one micron, the second conductive layer of the gate stack having opposing outer lateral edges which are recessed laterally within the opposing outer lateral edges of the first conductive layer and which are thereby spaced apart less than the opposing outer lateral edges of the first conductive layer are spaced apart, the insulative cap having opposing outer lateral edges in a final circuit construction of the transistor, the insulative cap having a topmost surface; and

a continuously extending oxide layer formed over the insulative cap topmost surface and laterally over each of the outer lateral edges of the first conductive layer, over each of the outer lateral edges of the second conductive layer and over each of the outer lateral edges of the insulative cap in the final circuit construction of the transistor;

the oxide layer in the final circuit construction of the transistor having opposing substantially continuous straight linear outermost lateral edges extending laterally along and laterally overlapping with all of each of the opposing outer lateral edges of the insulative cap and all of each of the opposing outer lateral edges of the second conductive layer.

2. The transistor of claim 1 wherein the opposing linear outer lateral edges of the oxide layer are formed to be less than 1 micron apart.

3. The transistor of claim 1 wherein the oxide layer has a lateral thickness of less than 100 Angstroms over the first conductive layer.

4. The transistor of claim 1 wherein the oxide layer has a lateral thickness of less than 100 Angstroms and greater than 10 Angstroms over the first conductive layer.

5. The transistor of claim 1 further comprising an insulative spacer formed laterally over the oxide layer.

6. The transistor of claim 1 further comprising an insulative spacer formed laterally over the oxide layer;

the insulative spacer extending laterally along portions of each of the insulative cap, the first conductive layer, and the second conductive layer.

7. The transistor of claim 1 further comprising an insulative spacer formed laterally over the oxide layer, the insulative spacer being laterally narrower at its topmost portion as compared to its lowestmost portion.

8. The transistor of claim 1 further comprising an insulative spacer formed laterally over the oxide layer;

the insulative spacer extending laterally along portions of each of the insulative cap, the first conductive layer, and the second conductive layer; and

the insulative spacer being laterally narrower at its topmost portion as compared to its lowestmost portion.