Structure and method for a compact trench-capacitor DRAM cell with body contact

• US 6,576,945 B2
• Filed: 02/05/2001
• Issued: 06/10/2003
• Est. Priority Date: 02/05/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Radens, Carl J., Mandelman, Jack A.
• Primary Examiner(s): Nguyen, Cuong Quang
• Application Number:
  US09/777,576
• Publication Number:
  US 20020105019A1
• Time in Patent Office: 855 Days
• Field of Search: 257/295-310, 438/241-253
• US Class Current: 257/301
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical

Abstract

A compact DRAM cell array that substantially minimizes floating-body effects and device-to-device interactions is disclosed. The compact DRAM cell array includes a plurality of annular memory cells that are arranged in rows and columns. Each annular memory cell includes a vertical MOSFET and an underlying capacitor that are in electrical contact to each other through a buried-strap outdiffusion region which is present within a portion of a wall of each annular memory cell such that the portion partially encircles the wall. The remaining portions of the wall of each annular memory cell have a body contact region that serves to electrically connect the annular memory cell to an adjacent array well region. The DRAM cell array also includes a plurality of wordlines overlaying the vertical MOSFETs, and a plurality of bitlines that are orthogonal to the plurality of wordlines.

Claims

1. A compact DRAM cell array which comprises:

a plurality of annular memory cells, which are arranged in rows and columns, each annular memory cell positioned within a trench and including a vertical MOSFET and an underlying capacitor surrounded by an annular ring wherein said vertical MOSFET and said underlying capacitor are in electrical contact to each other through a buried-strap outdiffusion region which is present within a portion of said annular ring of each annular memory cell such that said portion partially encircles said annular memory cell, the remaining portions of said annular ring of each annular memory cell have a body contact region which serves to electrically connect said annular memory cell to an adjacent array well region, said annular ring of each annular memory cell is self-aligned to said trench;

a plurality of wordlines overlaying said vertical MOSFETS, said plurality of wordlines being arranged in said row direction; and

a plurality of bitlines that are orthogonal to said plurality of wordlines.

2. The compact DRAM cell array of claim 1 wherein buried-strap outdiffusion regions of adjacent annular memory cells that are arranged in said columns are facing each other.

3. The compact DRAM cell array of claim 1 wherein buried-strap outdiffusion regions of adjacent annular memory cells in said columns are not facing each other.

4. The compact DRAM cell array of claim 1 wherein buried-strap outdiffusion regions of adjacent annular memory cells in said columns are facing each other,

whereas the neighboring pair of annular memory cells in said rows have buried-strap outdiffusion regions that are not facing each other.

5. The compact DRAM cell array of claim 1 further comprising bitline contacts which are formed between adjacent memory cells.

6. The compact DRAM cell array of claim 1 wherein an active area annulus surrounds each annular memory cell.

7. The compact DRAM cell array of claim 6 wherein isolation regions encircle said active area annulus of each annular memory cell.

8. The compact DRAM cell array of claim 1 wherein said buried-strap outdiffusion is partially connected to a collar oxide region which includes a divot region.

9. The compact DRAM cell array of claim 8 wherein said divot region is filled with polysilicon.

10. The compact DRAM cell array of claim 1 wherein diffusion regions encircle a portion of each annular memory cell.

11. The compact DRAM cell array of claim 1 wherein said plurality of annular memory cells have a cell area of sub-8F².

12. The compact DRAM cell array of claim 1 wherein said vertical MOSFETs include gate dielectrics formed on inner surfaces of said walls of said annular memory cell.

13. The compact DRAM cell array of claim 1 wherein adjacent buried-strap outdiffusion regions are electrically isolated from each other.

14. The compact DRAM cell of claim 1 wherein each vertical MOSFET has a body which is contained within a cylindrical shell such that a cross-section of the vertical MOSFET in a plane perpendicular to an axis of the cylindrical shell is an annulus.