Trench DMOS structure with peripheral trench with no source regions

• US 6,576,952 B2
• Filed: 01/17/2002
• Issued: 06/10/2003
• Est. Priority Date: 07/17/2000
• Status: Active Grant

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Tsui, Yan Man
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US10/051,504
• Publication Number:
  US 20020093048A1
• Time in Patent Office: 509 Days
• Field of Search: 257/328-331, 257/333, 257/334, 257/341, 257/401
• US Class Current: 257/328
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided. The structure comprises: (1) a substrate of a first conductivity type; (2) a body region on the substrate having a second conductivity type, wherein the peripheral and internal trenches extend through the body region; (3) an insulating layer that lines each of the peripheral and internal trenches; (4) a first conductive electrode overlying each insulating layer; and (5) source regions of the first conductivity type in the body region adjacent to the each internal trench, but not adjacent to the at least one peripheral trench.

Claims

1. A trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches, comprising:

a substrate of a first conductivity type;

a body region on the substrate, said body region having a second conductivity type, said peripheral and internal trenches extending through the body region;

an insulating layer that lines each of the peripheral and internal trenches;

a first conductive electrode overlying each insulating layer;

an insulating region overlying each first conductive electrode in said internal trenches, but no insulating region overlying the first conductive electrode in said at least one peripheral trench; and

source regions of the first conductivity type in the body region adjacent to said each internal trench, but not adjacent to said at least one peripheral trench.

2. The trench DMOS transistor structure of claim 1, wherein the first conductivity type is n-type conductivity and the second conductivity type is p-type conductivity.

3. The trench DMOS transistor structure of claim 1, further comprising a drain electrode disposed on a surface of the substrate opposing the body region and a source electrode disposed over at least a portion of the source regions.

4. The trench DMOS transistor structure of claim 1, wherein said insulating layer is an oxide layer.

5. The trench DMOS transistor structure of claim 1, wherein the insulating region is a borophosphosilicate glass structure.

6. The trench DMOS transistor structure of claim 1, wherein said conductive electrode comprises polysilicon.

7. The trench DMOS transistor structure of claim 1, further comprising a source electrode over and in contact with the first conductive electrode overlying the insulating layer in said at least one peripheral trench.