Trench MOSFET formed using selective epitaxial growth

• US 6,576,954 B2
• Filed: 02/06/2002
• Issued: 06/10/2003
• Est. Priority Date: 06/05/2000
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Madson, Gordon K., Sharp, Joelle
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US10/071,792
• Publication Number:
  US 20020102786A1
• Time in Patent Office: 489 Days
• Field of Search: 257/329, 257/330, 257/331, 257/333, 438/270
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of creating a thermally grown oxide of any thickness at the bottom of a silicon trench. A dielectric (e.g. oxide) pillar of a predetermined thickness is formed on a semiconductor substrate. A selective epitaxial growth (SEG) process is used to form an epitaxial layer around and over the oxide pillars. A trench is patterned and etched through the SEG layer and in alignment with the oxide pillar such that the trench terminates at the top of the oxide pillar.

Claims

1. A trench MOSFET, comprising:

a substrate having a first conductivity type;

a first semiconductor layer having the first conductivity type formed over the substrate;

a second semiconductor layer having the first conductivity type selectively formed over the first semiconductor layer;

a third semiconductor layer having a second conductivity type selectively formed over the second semiconductor layer;

a plurality of trenches extending from an exposed primary surface of the third semiconductor layer and through the third and second semiconductor layers, each trench defined by a bottom and walls;

a dielectric column positioned at the bottom of each trench, the column having a substantially flat upper surface and precisely controlled and predetermined thickness;

a dielectric material lining the walls of the trenches;

a conductive material lining the dielectric material and filling the trenches; and

dielectric caps formed over openings of the trenches, each cap having a top surface and lateral dimensions that are substantially the same as the lateral dimensions of the trenches.

2. The trench MOSFET of claim 1, further comprising a fourth semiconductor layer having the first conductivity type and a top surface that is substantially planar to the top surface of the dielectric caps.

3. The trench MOSFET of claim 2, further comprising heavily doped regions of the second conductivity type formed through the fourth semiconductor layer and partially within the third semiconductor layer.

4. The trench MOSFET of claim 2, wherein the fourth semiconductor layer is formed using selective epitaxial growth.

5. The trench MOSFET of claim 2, further comprising:

source regions having the first conductivity type next to each trench and within the fourth semiconductor layer.

6. The trench MOSFET of claim 5, further comprising:

heavily doped regions of the second conductivity type within the fourth semiconductor layer and between the source regions.

7. The trench MOSFET of claim 1, wherein the second semiconductor layer is formed using selective epitaxial growth.