Battery pack with monitoring function utilizing association with a battery charging system

• US 6,577,135 B1
• Filed: 04/09/2002
• Issued: 06/10/2003
• Est. Priority Date: 07/08/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Matthews, Wallace Edward, Landau, John Edward, Freeman, David Louis
• Primary Examiner(s): Oda, Christine
• Assistant Examiner(s): Hamdan, Wasseem H.
• Application Number:
  US10/119,385
• Time in Patent Office: 427 Days
• Field of Search: 324/426, 324/434, 324/427, 324/428, 324/429, 320/106, 320/112, 320/136, 320/152, 320/125, 320/108, 320/124, 320/135, 429/61, 429/93
• US Class Current: 324/426
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G01R 19/16542 for batteries charge condition monitoring in G01R31/36
• CPC Class Codes: G01R 31/374 with means for correcting the measurement for temperature or ageing
• CPC Class Codes: G01R 31/3832 without measurement of battery voltage
• CPC Class Codes: G01R 31/3835 involving only voltage measurements
• CPC Class Codes: H01M 10/425 Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing printed circuits H05K1/00
• CPC Class Codes: H01M 10/44 Methods for charging or discharging circuits for charging H02J7/00
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02J 7/00036 Charger exchanging data with battery
• CPC Class Codes: H02J 7/00047 with provisions for charging different types of batteries
• CPC Class Codes: H02J 7/00712 the cycle being controlled or terminated in response to electric parameters
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A battery detect circuit (32) is provided that is operable to dispose a sense resistor (50) in series with the battery to determine whether the charge is being provided to the battery or being extracted from the battery. The voltage across the sensor resistor (50) is sensed by a voltage/frequency converter (52). The voltage/frequency converter (52) is a differential structure comprised of two integrator structures (102) and (104) that are operable to utilize a switched capacitor configuration to drive comparators on the output thereof. Each of the integrator structures (102) and (104) has associated therewith passive elements and active elements. The integrators (102) and (104) have associated therewith integration capacitors (147) and (149). Additionally, there are two operational amplifiers (143) and (145) that provide the active components of each of the integrators (102) and (104). The various switched capacitor circuits (161) and (163) associated with the amplifiers (143) and (145) are provided to provide the integration operation. Both the amplifiers (143) and (145) and their associated switched capacitor circuits (161) and (163) are dynamically balanced such that they are switched between integrator (102) and integrator (104) on a periodic basis. This therefore allows the errors between the active and passive elements to be switched between the two integrators (102) and (104) such that no accumulative error occurs.

Claims

1. A battery monitoring circuit for monitoring current through a sense resistor disposed in series with one terminal of the battery by detecting the voltage across the sense resistor, comprising:

a voltage/frequency converter for converting the voltage across the sense resistor to a pulse stream, the rate of said pulse stream corresponding to the voltage across the sense resistors;

a circuit for determining the current through the terminal battery with the pulse stream, the current being a function of the rate of the pulse stream; and

said voltage/frequency converter having a differential structure associated therewith, said differential structure having;

a first differential leg having passive switching elements and active elements associated therewith for receiving as an input voltage the voltage that is across the sense resistor and outputting a first differential signal,

a second differential leg having passive switching elements and active elements associated therewith for receiving on an input the voltage across the sense resistor and outputting a second differential voltage, and

a multiplex circuit for periodically switching select portions of said switching elements and passive active elements between said first and second differential legs to compensate for errors integral therewith.

2. The monitoring circuit of claim 1, wherein:

each of said first and second differential legs having associated therewith first and second switched capacitor integrators, respectively, that each provide an integrated voltage on the output of the respective one of said first and second switched capacitor integrators that is a function of the input voltage input thereto, the input voltage applied thereto being voltage across the sense resistor;

said first switched capacitor integrator having a first integrator feedback capacitor associated therewith and first switched control signals;

said second switched capacitor integrator having a second integrator feedback capacitor associated therewith and second switched control signals;

a first switchable amplifier with an associated switched capacitor input structure which, when the first switchable amplifier has said first or second feedback capacitor connected between the input and output thereof and said associated switched capacitor input structure controlled by said first or second switched control signals will form said first or second switched capacitor integrator;

a second switchable amplifier with an associated switched capacitor input structure which, when said second switchable amplifier has said first or second feedback capacitor connected between the input and output thereof and said associated switched capacitor structure controlled by said first or second switched control signals will form said first or second switched capacitor integrator; and

said multiplex circuit operable to alternately switch said first and second switchable amplifiers between said first and second differential legs and said first and second integrated feedback capacitors.

3. A differential switched capacitor circuit for processing positive and negative differential input signals, comprising:

a first leg for receiving the positive differential input and having;

a first switched capacitor structure,

a first active element,

a first memory element, and

first switch control signals for controlling said first switched capacitor structure, said first switched capacitor structure, said first active element, said first memory element, and said first switch control signals operating to process the positive differential input and provide a positive differential output with a predetermined circuit configuration;

a second leg for receiving the negative differential input and having;

a second switched capacitor structure,

a second active element,

a second memory element, and

second switch control signals for controlling said second switched capacitor structure, said second switched capacitor structure, said second memory element, said second active element and said second switch control signals operating to process the negative differential input to provide a negative differential output in accordance with the predetermined circuit configuration; and

a multiplexing control system for periodically interchanging said first switched capacitor and first active element in said first leg with said second switched capacitor structure and said second active element in said second leg and then back without interchanging said first and second memory elements and said first and second switch control signals.

4. The differential switched capacitor circuit of claim 3, wherein said first and second memory elements are first and second capacitors, respectively.

5. The differential switched capacitor circuit of claim 4, wherein said predetermined circuit configuration is an integrator and said first and second capacitors comprise the integrating capacitors of the integrator structure with said first switched capacitor structure and said second switched capacitor structure providing input structure for the respective integrator structure.

6. The differential switched capacitor circuit of claim 3, wherein the switching operation of said first switch control signals and said second switch control signals is at a substantially higher rate than the rate at which said multiplexer control interchanges said first switched capacitor and first active element with said second switched capacitor and said second active element.

7. The differential switched capacitor circuit of claim 3, further comprising a summing device for summing the output of said first and second legs.