Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer

• US 6,577,148 B1
• Filed: 07/24/1995
• Issued: 06/10/2003
• Est. Priority Date: 08/31/1994
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: DeHaven, Robert Keith, Wenzel, James F.
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US08/506,292
• Time in Patent Office: 2,878 Days
• Field of Search: 324/754, 324/757, 324/158.1, 324/765, 324/758, 324/763, 439/91
• US Class Current: 324/762.05
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2849 Environmental or reliability testing, e.g. burn-in or validation tests of individual semiconductors G01R31/2642; of printed circuits boards G01R31/2817; of IC's G01R31/2855
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
• CPC Class Codes: G01R 31/2881 related to environmental aspects other than temperature, e.g. humidity or vibrations
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49162 by using wire as conductive path

Abstract

A method, apparatus, and circuit distribution wafer (CDW) (16) are used to wafer-level test a product wafer (14) containing one or more product integrated circuits (ICs). The CDW (16) contains circuitry which is used to test the ICs on the product wafers (14). A connection from the product wafer (14) to the CDW (16) is made via a compliant interconnect media (IM) (18). Through IM (18), the CDW (16) tests the product wafer (14) under any set of test conditions. Through external connectors and conductors (20, 22, 24, and 26) the CDW (16) transmits and receives test data, control information, temperature control, and the like from an external tester (104). To improve performance and testability, the CDW (16) and heating/cooling (80 and 82) of the wafers may be segmented into two or more wafer sections for greater control and more accurate testing.

Claims

1. A method for stimulating a product wafer using a stimulus wafer, the method comprising the steps of:

providing the product wafer wherein the product wafer comprises a plurality of product integrated circuits which are to be stimulated, the product wafer having a selectively exposed top conductive layer of material coupled to the product integrated circuits;

providing the stimulus wafer wherein the stimulus wafer comprises a plurality of stimulus circuits wherein at least one stimulus circuit within the plurality of stimulus circuits corresponds to one product integrated circuit within the plurality of product integrated circuits, the stimulus wafer having a selectively exposed top conductive layer of material coupled to the stimulus circuits; and

positioning a compliant interconnect media between product wafer and the stimulus wafer, the compliant interconnect media coupling the selectively exposed top conductive layer of material of the product wafer with the selectively exposed top conductive layer of material of the stimulus wafer to allow the stimulus wafer to stimulate the product wafer via electrical signals transmitted through the compliant interconnect media, the compliant interconnect media being a contiguous film of dielectric material which has conductive fibers formed therethrough;

wherein the stimulus wafer communicates to the product wafer a clock signal wherein the clock signal is used by the plurality of product integrated circuits as a functional clock signal.

2. A method for stimulating a product wafer using a stimulus wafer, the method comprising the steps of:

providing the product wafer wherein the product wafer comprises a plurality of product integrated circuits which are to be stimulated, the product wafer having a selectively exposed top conductive layer of material coupled to the product integrated circuits;

providing the stimulus wafer wherein the stimulus wafer comprises a plurality of stimulus circuits wherein at least one stimulus circuit within the plurality of stimulus circuits corresponds to one product integrated circuit within the plurality of product integrated circuits, the stimulus wafer having a selectively exposed top conductive layer of material coupled to the stimulus circuits; and

positioning a compliant interconnect media between product wafer and the stimulus wafer, the compliant interconnect media coupling the selectively exposed top conductive layer of material of the product wafer with the selectively exposed top conductive layer of material of the stimulus wafer to allow the stimulus wafer to stimulate the product wafer via electrical signals transmitted through the compliant interconnect media, the compliant interconnect media being a contiguous film of dielectric material which has conductive fibers formed therethrough;

wherein the stimulus wafer communicates to the product wafer a reset signal wherein the reset signal forces the plurality of product integrated circuits into a reset state.

3. A method for stimulating a product wafer using a stimulus wafer, the method comprising the steps of:

providing a product wafer having a plurality of product integrated circuits formed on a major surface of the product wafer;

providing a stimulus wafer containing a plurality of stimulus integrated circuits formed on a major surface of eh stimulus wafer;

connecting the major surface of the product wafer to the major surface of the stimulus wafer via a compliant interconnect media wherein the compliant interconnect media is a dielectric material having a plurality of conductive fibers formed therethrough, the plurality of conductive fibers coupling the plurality of product integrated circuits to the plurality of stimulus integrated circuits;

electrically coupling the stimulus wafer to an external tester so that the external tester can communicate information to the stimulus wafer and receive information from the stimulus wafer; and

changing the temperature of product wafer to a stimulus temperature; and

testing the plurality of product integrate circuits by communicating test information from the plurality of stimulus integrated circuits to the plurality of product integrated circuits;

wherein the test information includes a clock signal transmitted from the stimulus wafer to the product wafer through the plurality of conductive fibers.

4. A method for stimulating a product wafer using a stimulus wafer, the method comprising the steps of:

providing a product wafer having a plurality of product integrated circuits formed on a major surface of the product wafer;

providing a stimulus wafer containing a plurality of stimulus integrated circuits formed on a major surface of eh stimulus wafer;

connecting the major surface of the product wafer to the major surface of the stimulus wafer via a compliant interconnect media wherein the compliant interconnect media is a dielectric material having a plurality of conductive fibers formed therethrough, the plurality of conductive fibers coupling the plurality of product integrated circuits to the plurality of stimulus integrated circuits;

electrically coupling the stimulus wafer to an external tester so that the external tester can communicate information to the stimulus wafer and receive information from the stimulus wafer; and

changing the temperature of product wafer to a stimulus temperature; and

testing the plurality of product integrate circuits by communicating test information from the plurality of stimulus integrated circuits to the plurality of product integrated circuits;

wherein the test information includes a reset signal transmitted from the stimulus wafer to the product wafer through the plurality of conductive fibers to allow the plurality of product integrated circuits to be placed into a reset state.

5. A method for stimulating a product wafer using a stimulus wafer, the method comprising the steps of:

providing a product wafer having a plurality of product integrated circuits formed on a major surface of the product wafer, the plurality of product integrated circuits containing logic circuitry coupled to a top layer of exposed conductive regions;

providing a stimulus wafer containing a plurality of stimulus integrated circuits formed on a major surface of the stimulus wafer, the plurality of stimulus integrated circuits on the stimulus wafer being intercoupled by several conductive lines that run across a substantial length of the major surface of the stimulus wafer, the stimulus wafer also containing contact areas which are coupled to wires wherein the wires are used to communicate information external to the stimulus wafer, the plurality of stimulus integrated circuits containing logic circuitry coupled to a top layer of exposed conductive regions;

connecting the top layer of exposed conductive regions of the product wafer to the top layer of exposed conductive regions of the stimulus wafer via a compliant interconnect media where the compliant interconnect media is a dielectric material having a plurality of conductive fibers formed therethrough, the plurality of conductive fibers allowing electrical signals to be communicated to or form the plurality of product integrated circuits to or from the plurality of stimulus integrated circuits, the compliant interconnect media coupled to the stimulus wafer to the product wafer in a manner wherein the major surface of the stimulus wafer faces the major surface of the product wafer;

electrically coupling the stimulus wafer to an external tester via the wires so that the external tester can communicate information to the stimulus wafer and receive information from the stimulus wafer;

changing the temperature of the product wafer to a stimulus temperature; and

testing the plurality of product integrated circuits by communicating test information from the plurality of stimulus integrated circuits to the plurality of product integrated circuits;

wherein the test information includes a clock signal transmitted from the stimulus wafer to the product wafer through the plurality of conductive fibers.

6. A method for stimulating a product wafer using a stimulus wafer, the method comprising the steps of:

providing a product wafer having a plurality of product integrated circuits formed on a major surface of the product wafer, the plurality of product integrated circuits containing logic circuitry coupled to a top layer of exposed conductive regions;

providing a stimulus wafer containing a plurality of stimulus integrated circuits formed on a major surface of the stimulus wafer, the plurality of stimulus integrated circuits on the stimulus wafer being intercoupled by several conductive lines that run across a substantial length of the major surface of the stimulus wafer, the stimulus wafer also containing contact areas which are coupled to wires wherein the wires are used to communicate information external to the stimulus wafer, the plurality of stimulus integrated circuits containing logic circuitry coupled to a top layer of exposed conductive regions;

connecting the top layer of exposed conductive regions of the product wafer to the top layer of exposed conductive regions of the stimulus wafer via a compliant interconnect media where the compliant interconnect media is a dielectric material having a plurality of conductive fibers formed therethrough, the plurality of conductive fibers allowing electrical signals to be communicated to or form the plurality of product integrated circuits to or from the plurality of stimulus integrated circuits, the compliant interconnect media coupled to the stimulus wafer to the product wafer in a manner wherein the major surface of the stimulus wafer faces the major surface of the product wafer;

electrically coupling the stimulus wafer to an external tester via the wires so that the external tester can communicate information to the stimulus wafer and receive information from the stimulus wafer;

changing the temperature of the product wafer to a stimulus temperature; and

testing the plurality of product integrated circuits by communicating test information from the plurality of stimulus integrated circuits to the plurality of product integrated circuits;

wherein the test information includes a reset signal transmitted from the stimulus wafer to the product wafer through the plurality of conductive fibers to allow the plurality of product integrated circuits to be placed into a reset state.