Uni-sized clock buffers

• US 6,577,165 B1
• Filed: 10/25/2001
• Issued: 06/10/2003
• Est. Priority Date: 10/25/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Au, Keith D., Cheung, Cyrus C.
• Primary Examiner(s): CHANG, DANIEL D
• Application Number:
  US10/027,960
• Time in Patent Office: 593 Days
• Field of Search: 326/93, 326/101, 326/47, 327/295, 327/297
• US Class Current: 326/93
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

A system which simplifies the clock tuning process for a clock buffer tree. Essentially, a clock buffer tree is provided where the clock buffer tree includes clock buffers of different strengths. The different strength clock buffers which are in the clock buffer tree have the same pin-out configuration. Hence, it is easy and straightforward to upsize or downsize any of the clock buffers in the clock buffer tree, and it is guaranteed that the new cell will fit into the old cell'"'"'s slot in the tree. Since none of the nets need to be modified, consistent timing results are achieved. Moreover, the new timing for the modified clock buffer can be anticipated because its wire loading does not change at all. The ease of clock tuning makes it much easier to design clock buffer trees and layouts, and allows the overall design to be completed faster and easier.

Claims

1. A clock buffer tree comprising:

a plurality of cells having different drive strength clock buffers, each cell having identical pin-out configurations,

wherein each of said plurality of cells identical in size and is interchangeable with another one of said plurality of cells such that a strength of said clock buffer tree is changeable without requiring wiring redesign.

2. A clock buffer tree as recited in claim 1, wherein the clock buffer tree comprises a first cell connected to less than six Flip-Flops, and a second cell connected to more than sixty Flip-Flops, wherein the first cell has a lower drive strength than the second cell, and wherein the first and second cells have the same pin-out configuration and said first cell is interchangeable with said second cell.

3. A clock buffer tree comprising:

a first cell connected to a set of five Flip-Flops;

a second cell connected to a set of eleven Flip-Flops;

a third cell connected to a set of thirty-two Flip-Flops;

a fourth cell connected to a set of sixty-four Flip-Flops, wherein the first cell has a lower drive strength than the second cell, wherein the second cell has a lower drive strength than the third cell, wherein the third cell has a lower drive strength than the fourth cell, and wherein the first, second, third and fourth cells have the same pin-out configuration, are the same size and are interchangeable such that when said cells are interchanged, wiring redesign is not required.

4. A method of designing a clock buffer tree comprising:

designing an initial version of the clock buffer tree wherein the clock buffer tree includes a plurality of cells having different drive strengths but the same pin-out configuration and wherein each of said plurality of cells is the same size; and

upsizing or downsizing a drive strength of an unwanted cells in the clock buffer tree by replacing the unwanted cell with a new cell, wherein the new cell has a different drive strength than the unwanted cell, but has the same pin-out configuration as the unwanted cell and wherein said new cell is the same size as said unwanted cell and wiring redesign is not required.